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authorYann Herklotz <git@ymhg.org>2019-04-02 18:16:21 +0100
committerYann Herklotz <git@ymhg.org>2019-04-02 18:16:21 +0100
commitc0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch)
tree042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz.hs
parent1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff)
downloadverismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz
verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz.hs')
-rw-r--r--src/VeriFuzz.hs4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz.hs b/src/VeriFuzz.hs
index d07c26e..6099c28 100644
--- a/src/VeriFuzz.hs
+++ b/src/VeriFuzz.hs
@@ -77,7 +77,7 @@ generateByteString n = do
makeSrcInfo :: ModDecl -> SourceInfo
makeSrcInfo m =
- SourceInfo (m ^. modId . getIdentifier) (VerilogSrc [Description m])
+ SourceInfo (m ^. modId . getIdentifier) (Verilog [Description m])
-- | Draw a randomly generated DAG to a dot file and compile it to a png so it
-- can be seen.
@@ -100,7 +100,7 @@ runSimulation = do
-- writeFile "file.dot" dot
-- shelly $ run_ "dot" ["-Tpng", "-o", "file.png", "file.dot"]
-- let circ =
- -- head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilogSrc . traverse . getDescription
+ -- head $ (nestUpTo 30 . generateAST $ Circuit gr) ^.. getVerilog . traverse . getDescription
rand <- generateByteString 20
rand2 <- Hog.sample (randomMod 10 100)
val <- shelly $ runSim defaultIcarus (makeSrcInfo rand2) rand