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author | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
commit | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch) | |
tree | 042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/AST.hs | |
parent | 1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff) | |
download | verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip |
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/AST.hs')
-rw-r--r-- | src/VeriFuzz/AST.hs | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/VeriFuzz/AST.hs b/src/VeriFuzz/AST.hs index 0f877f3..1381cc1 100644 --- a/src/VeriFuzz/AST.hs +++ b/src/VeriFuzz/AST.hs @@ -16,8 +16,8 @@ Defines the types to build a Verilog AST. module VeriFuzz.AST ( -- * Top level types - VerilogSrc(..) - , getVerilogSrc + Verilog(..) + , getVerilog , Description(..) , getDescription -- * Primitives @@ -396,7 +396,7 @@ newtype Description = Description { _getDescription :: ModDecl } deriving (Eq, Show, Ord, Data) -- | The complete sourcetext for the Verilog module. -newtype VerilogSrc = VerilogSrc { _getVerilogSrc :: [Description] } +newtype Verilog = Verilog { _getVerilog :: [Description] } deriving (Eq, Show, Ord, Data, Semigroup, Monoid) makeLenses ''Identifier @@ -414,13 +414,13 @@ makeLenses ''Statement makeLenses ''ModItem makeLenses ''ModDecl makeLenses ''Description -makeLenses ''VerilogSrc +makeLenses ''Verilog -getModule :: Traversal' VerilogSrc ModDecl -getModule = getVerilogSrc . traverse . getDescription +getModule :: Traversal' Verilog ModDecl +getModule = getVerilog . traverse . getDescription {-# INLINE getModule #-} -getSourceId :: Traversal' VerilogSrc Text +getSourceId :: Traversal' Verilog Text getSourceId = getModule . modId . getIdentifier {-# INLINE getSourceId #-} @@ -610,8 +610,8 @@ instance Arb ModDecl where instance Arb Description where arb = Description <$> arb -instance Arb VerilogSrc where - arb = VerilogSrc <$> listOf1 arb +instance Arb Verilog where + arb = Verilog <$> listOf1 arb instance Arb Bool where arb = Hog.element [True, False] |