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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 20:19:00 +0000 |
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| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 20:19:00 +0000 |
| commit | 5025a43948a682bc40d5c91606ec97cd8d6c3897 (patch) | |
| tree | b31c5113ff0a7d93424ba21a6c288f704f24dc78 /src/VeriFuzz/ASTGen.hs | |
| parent | a180c89947f8e0c191ba7e7dba4c6eb7edf538e6 (diff) | |
| download | verismith-5025a43948a682bc40d5c91606ec97cd8d6c3897.tar.gz verismith-5025a43948a682bc40d5c91606ec97cd8d6c3897.zip | |
Change Port type, adding signed info
Diffstat (limited to 'src/VeriFuzz/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/ASTGen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index 6bac157..ff948c3 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -38,7 +38,7 @@ inputsC :: Circuit -> [Node] inputsC c = inputs (getCircuit c) genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] -genPortsAST f c = port . frNode <$> f c where port = Port Wire 4 +genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4 -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. @@ -71,7 +71,7 @@ genModuleDeclAST c = ModDecl i output ports items where i = Identifier "gen_module" ports = genPortsAST inputsC c - output = [Port Wire 90 "y"] + output = [Port Wire False 90 "y"] a = genAssignAST c items = a ++ [ModCA . ContAssign "y" . fold $ Id <$> assigns] assigns = a ^.. traverse . modContAssign . contAssignNetLVal |