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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 14:28:30 +0000 |
|---|---|---|
| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-16 14:28:30 +0000 |
| commit | f28188fc54d187b501b861d43592702bc7e460ec (patch) | |
| tree | c1d898d080dcfa44a5461218a047d04883076a23 /src/VeriFuzz/ASTGen.hs | |
| parent | a83b3b40f683400914d0f3ae23bd9e69e6e0fd96 (diff) | |
| download | verismith-f28188fc54d187b501b861d43592702bc7e460ec.tar.gz verismith-f28188fc54d187b501b861d43592702bc7e460ec.zip | |
Add export lists
Diffstat (limited to 'src/VeriFuzz/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/ASTGen.hs | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index d113bbb..6bac157 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -10,7 +10,9 @@ Portability : POSIX Generates the AST from the graph directly. -} -module VeriFuzz.ASTGen where +module VeriFuzz.ASTGen + ( generateAST + ) where import Control.Lens ((^..)) import Data.Foldable (fold) @@ -35,9 +37,6 @@ fromGate Xor = BinXor inputsC :: Circuit -> [Node] inputsC c = inputs (getCircuit c) -outputsC :: Circuit -> [Node] -outputsC c = outputs (getCircuit c) - genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] genPortsAST f c = port . frNode <$> f c where port = Port Wire 4 |