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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 11:41:38 +0000 |
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| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 11:41:38 +0000 |
| commit | 0ea6e208f2c3c41922f8334174fc8e81a21d67f4 (patch) | |
| tree | 3c4889aff5a85f58f7d4db296d7f2f26b8ad031f /src/VeriFuzz/ASTGen.hs | |
| parent | 08b2b306ae1accfa0b84dc3d327ba54add10a284 (diff) | |
| download | verismith-0ea6e208f2c3c41922f8334174fc8e81a21d67f4.tar.gz verismith-0ea6e208f2c3c41922f8334174fc8e81a21d67f4.zip | |
Brittany formatting
Diffstat (limited to 'src/VeriFuzz/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/ASTGen.hs | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/VeriFuzz/ASTGen.hs b/src/VeriFuzz/ASTGen.hs index ff948c3..ab097e4 100644 --- a/src/VeriFuzz/ASTGen.hs +++ b/src/VeriFuzz/ASTGen.hs @@ -12,7 +12,8 @@ Generates the AST from the graph directly. module VeriFuzz.ASTGen ( generateAST - ) where + ) +where import Control.Lens ((^..)) import Data.Foldable (fold) @@ -69,11 +70,11 @@ genAssignAST c = catMaybes $ genContAssignAST c <$> nodes genModuleDeclAST :: Circuit -> ModDecl genModuleDeclAST c = ModDecl i output ports items where - i = Identifier "gen_module" - ports = genPortsAST inputsC c - output = [Port Wire False 90 "y"] - a = genAssignAST c - items = a ++ [ModCA . ContAssign "y" . fold $ Id <$> assigns] + i = Identifier "gen_module" + ports = genPortsAST inputsC c + output = [Port Wire False 90 "y"] + a = genAssignAST c + items = a ++ [ModCA . ContAssign "y" . fold $ Id <$> assigns] assigns = a ^.. traverse . modContAssign . contAssignNetLVal generateAST :: Circuit -> VerilogSrc |