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| author | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:22:34 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:22:34 +0100 |
| commit | 8125f2c36d6306e20ce78f4056ef1b2fb6de61a2 (patch) | |
| tree | 67ca1b50ef43756a2e2283096866d044ac29891a /src/VeriFuzz/Circuit.hs | |
| parent | c17753e6f43ecb46dba09db4d655cae5dd8e7b5c (diff) | |
| download | verismith-8125f2c36d6306e20ce78f4056ef1b2fb6de61a2.tar.gz verismith-8125f2c36d6306e20ce78f4056ef1b2fb6de61a2.zip | |
Changes to general types
Diffstat (limited to 'src/VeriFuzz/Circuit.hs')
| -rw-r--r-- | src/VeriFuzz/Circuit.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriFuzz/Circuit.hs index d385d32..58027b1 100644 --- a/src/VeriFuzz/Circuit.hs +++ b/src/VeriFuzz/Circuit.hs @@ -41,5 +41,5 @@ fromGraph = do $ initMod . head $ nestUpTo 5 (generateAST gr) - ^.. getVerilog + ^.. _Wrapped . traverse |