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author | Yann Herklotz <git@ymhg.org> | 2019-04-02 19:47:32 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 19:47:32 +0100 |
commit | fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0 (patch) | |
tree | 673439d49fa095bf3ae9b7bbbca5f30d7ff20838 /src/VeriFuzz/Circuit.hs | |
parent | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (diff) | |
download | verismith-fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0.tar.gz verismith-fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0.zip |
Large refactor with passing tests
Diffstat (limited to 'src/VeriFuzz/Circuit.hs')
-rw-r--r-- | src/VeriFuzz/Circuit.hs | 47 |
1 files changed, 25 insertions, 22 deletions
diff --git a/src/VeriFuzz/Circuit.hs b/src/VeriFuzz/Circuit.hs index af534a2..37e25ac 100644 --- a/src/VeriFuzz/Circuit.hs +++ b/src/VeriFuzz/Circuit.hs @@ -16,28 +16,31 @@ module VeriFuzz.Circuit , Circuit(..) , CNode(..) , CEdge(..) + , fromGraph + , generateAST + , rDups + , rDupsCirc + , randomDAG + , genRandomDAG ) where -import Data.Graph.Inductive (Gr, LEdge, LNode) -import System.Random - --- | The types for all the gates. -data Gate = And - | Or - | Xor - deriving (Show, Eq, Enum, Bounded, Ord) - --- | Newtype for the Circuit which implements a Graph from fgl. -newtype Circuit = Circuit { getCircuit :: Gr Gate () } - -newtype CNode = CNode { getCNode :: LNode Gate } - -newtype CEdge = CEdge { getCEdge :: LEdge () } - -instance Random Gate where - randomR (a, b) g = - case randomR (fromEnum a, fromEnum b) g of - (x, g') -> (toEnum x, g') - - random = randomR (minBound, maxBound) +import Control.Lens +import Hedgehog (Gen) +import qualified Hedgehog.Gen as Hog +import VeriFuzz.Circuit.Base +import VeriFuzz.Circuit.Gen +import VeriFuzz.Circuit.Random +import VeriFuzz.Verilog.AST +import VeriFuzz.Verilog.Mutate + +fromGraph :: Gen ModDecl +fromGraph = do + gr <- rDupsCirc <$> Hog.resize 100 randomDAG + return + $ initMod + . head + $ nestUpTo 5 (generateAST gr) + ^.. getVerilog + . traverse + . getDescription |