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| author | Yann Herklotz <git@yannherklotz.com> | 2019-07-23 22:05:32 +0200 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-23 22:05:41 +0200 |
| commit | 992e91427fccff43f8ab1944131b8f62f9328f0d (patch) | |
| tree | 1108e017b2c172da02dde8d07d17f0eda7bc23f9 /src/VeriFuzz/Circuit/Gen.hs | |
| parent | 24382ce10ed53724ad2d097a7ed2397806be3e67 (diff) | |
| download | verismith-992e91427fccff43f8ab1944131b8f62f9328f0d.tar.gz verismith-992e91427fccff43f8ab1944131b8f62f9328f0d.zip | |
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Diffstat (limited to 'src/VeriFuzz/Circuit/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 323d8bb..eb7cb97 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -3,7 +3,7 @@ Module : Verilog.Circuit.Gen Description : Generate verilog from circuit. Copyright : (c) 2019, Yann Herklotz Grave License : GPL-3 -Maintainer : ymherklotz [at] gmail [dot] com +Maintainer : yann [at] yannherklotz [dot] com Stability : experimental Portability : POSIX @@ -15,11 +15,9 @@ module VeriFuzz.Circuit.Gen ) where -import Data.Graph.Inductive ( LNode - , Node - ) -import qualified Data.Graph.Inductive as G -import Data.Maybe ( catMaybes ) +import Data.Graph.Inductive (LNode, Node) +import qualified Data.Graph.Inductive as G +import Data.Maybe (catMaybes) import VeriFuzz.Circuit.Base import VeriFuzz.Circuit.Internal import VeriFuzz.Verilog.AST |