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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-29 20:33:59 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-29 20:33:59 +0100 |
| commit | d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094 (patch) | |
| tree | 9aee938477a884daa20148b56fc1feef52d4f2c4 /src/VeriFuzz/Circuit/Gen.hs | |
| parent | bb697f8bc7b593e5aabb43505f686e6503b7726f (diff) | |
| download | verismith-d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094.tar.gz verismith-d32f4cc45bc8c0670fb788b1fcd4c2f2b15fa094.zip | |
Format files
Diffstat (limited to 'src/VeriFuzz/Circuit/Gen.hs')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 0b13ece..323d8bb 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -15,9 +15,11 @@ module VeriFuzz.Circuit.Gen ) where -import Data.Graph.Inductive (LNode, Node) -import qualified Data.Graph.Inductive as G -import Data.Maybe (catMaybes) +import Data.Graph.Inductive ( LNode + , Node + ) +import qualified Data.Graph.Inductive as G +import Data.Maybe ( catMaybes ) import VeriFuzz.Circuit.Base import VeriFuzz.Circuit.Internal import VeriFuzz.Verilog.AST |