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authorYann Herklotz <git@yannherklotz.com>2019-08-29 15:44:33 +1000
committerYann Herklotz <git@yannherklotz.com>2019-08-29 15:44:33 +1000
commitcccb665ebac6e916c4f961eacbe11a9af7d7ceb3 (patch)
treef00baaec9dcb747c27375af366ad9aec9d2dbe16 /src/VeriFuzz/Circuit/Gen.hs
parent74a14ef30359e653259bf7139fe806548edefd14 (diff)
downloadverismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.tar.gz
verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.zip
Change name from VeriFuzz to VeriSmith
Diffstat (limited to 'src/VeriFuzz/Circuit/Gen.hs')
-rw-r--r--src/VeriFuzz/Circuit/Gen.hs16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs
index eb7cb97..1c4dd37 100644
--- a/src/VeriFuzz/Circuit/Gen.hs
+++ b/src/VeriFuzz/Circuit/Gen.hs
@@ -10,18 +10,18 @@ Portability : POSIX
Generate verilog from circuit.
-}
-module VeriFuzz.Circuit.Gen
+module VeriSmith.Circuit.Gen
( generateAST
)
where
-import Data.Graph.Inductive (LNode, Node)
-import qualified Data.Graph.Inductive as G
-import Data.Maybe (catMaybes)
-import VeriFuzz.Circuit.Base
-import VeriFuzz.Circuit.Internal
-import VeriFuzz.Verilog.AST
-import VeriFuzz.Verilog.Mutate
+import Data.Graph.Inductive (LNode, Node)
+import qualified Data.Graph.Inductive as G
+import Data.Maybe (catMaybes)
+import VeriSmith.Circuit.Base
+import VeriSmith.Circuit.Internal
+import VeriSmith.Verilog.AST
+import VeriSmith.Verilog.Mutate
-- | Converts a 'CNode' to an 'Identifier'.
frNode :: Node -> Identifier