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| author | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:22:34 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:22:34 +0100 |
| commit | 8125f2c36d6306e20ce78f4056ef1b2fb6de61a2 (patch) | |
| tree | 67ca1b50ef43756a2e2283096866d044ac29891a /src/VeriFuzz/Circuit | |
| parent | c17753e6f43ecb46dba09db4d655cae5dd8e7b5c (diff) | |
| download | verismith-8125f2c36d6306e20ce78f4056ef1b2fb6de61a2.tar.gz verismith-8125f2c36d6306e20ce78f4056ef1b2fb6de61a2.zip | |
Changes to general types
Diffstat (limited to 'src/VeriFuzz/Circuit')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 1e31e56..0b13ece 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -38,7 +38,7 @@ inputsC :: Circuit -> [Node] inputsC c = inputs (getCircuit c) genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] -genPortsAST f c = port . frNode <$> f c where port = Port Wire False 0 4 +genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4 -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. @@ -73,7 +73,7 @@ genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) [] ports = genPortsAST inputsC c output = [] a = genAssignAST c - yPort = Port Wire False 0 90 "y" + yPort = Port Wire False 90 "y" generateAST :: Circuit -> Verilog generateAST c = Verilog [genModuleDeclAST c] |