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| author | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
| commit | d350cd339797c6dd9056afa2b1dad5aed4c31cb9 (patch) | |
| tree | 868474f18dfedc05d347cf16d09b5e770bc33293 /src/VeriFuzz/Circuit | |
| parent | 7653f8fd33162b8b166a12e125c988663ec2fe79 (diff) | |
| download | verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.tar.gz verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.zip | |
Add Parameter type and remove Description
Diffstat (limited to 'src/VeriFuzz/Circuit')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 817d2f8..0b13ece 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -67,7 +67,7 @@ genAssignAST c = catMaybes $ genContAssignAST c <$> nodes nodes = G.labNodes gr genModuleDeclAST :: Circuit -> ModDecl -genModuleDeclAST c = ModDecl i output ports $ combineAssigns yPort a +genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) [] where i = Identifier "gen_module" ports = genPortsAST inputsC c @@ -76,4 +76,4 @@ genModuleDeclAST c = ModDecl i output ports $ combineAssigns yPort a yPort = Port Wire False 90 "y" generateAST :: Circuit -> Verilog -generateAST c = Verilog [Description $ genModuleDeclAST c] +generateAST c = Verilog [genModuleDeclAST c] |