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| author | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:24 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-12 17:16:24 +0100 |
| commit | d695414e67f9adb7f665602a20a898fa77eba106 (patch) | |
| tree | d22e902e4e34b5c4385f0c863da6e71803903613 /src/VeriFuzz/Circuit | |
| parent | e22a59ad643ac2fe96b0c11208651a6f7a6605b0 (diff) | |
| download | verismith-d695414e67f9adb7f665602a20a898fa77eba106.tar.gz verismith-d695414e67f9adb7f665602a20a898fa77eba106.zip | |
Change Port type to include lower bound
Diffstat (limited to 'src/VeriFuzz/Circuit')
| -rw-r--r-- | src/VeriFuzz/Circuit/Gen.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Circuit/Gen.hs b/src/VeriFuzz/Circuit/Gen.hs index 0b13ece..1e31e56 100644 --- a/src/VeriFuzz/Circuit/Gen.hs +++ b/src/VeriFuzz/Circuit/Gen.hs @@ -38,7 +38,7 @@ inputsC :: Circuit -> [Node] inputsC c = inputs (getCircuit c) genPortsAST :: (Circuit -> [Node]) -> Circuit -> [Port] -genPortsAST f c = port . frNode <$> f c where port = Port Wire False 4 +genPortsAST f c = port . frNode <$> f c where port = Port Wire False 0 4 -- | Generates the nested expression AST, so that it can then generate the -- assignment expressions. @@ -73,7 +73,7 @@ genModuleDeclAST c = ModDecl i output ports (combineAssigns yPort a) [] ports = genPortsAST inputsC c output = [] a = genAssignAST c - yPort = Port Wire False 90 "y" + yPort = Port Wire False 0 90 "y" generateAST :: Circuit -> Verilog generateAST c = Verilog [genModuleDeclAST c] |