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author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-03-01 12:30:51 +0000 |
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committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-03-01 12:30:51 +0000 |
commit | 1f05f1050389917edeb64c0b32391da2f8ebe40b (patch) | |
tree | 820d019d0c9a1670415e89d77a588d6aa675a17e /src/VeriFuzz/CodeGen.hs | |
parent | 7f1b3462024211eebeb609d4b4ab055d4bb738fa (diff) | |
download | verismith-1f05f1050389917edeb64c0b32391da2f8ebe40b.tar.gz verismith-1f05f1050389917edeb64c0b32391da2f8ebe40b.zip |
Fix indentation
Diffstat (limited to 'src/VeriFuzz/CodeGen.hs')
-rw-r--r-- | src/VeriFuzz/CodeGen.hs | 41 |
1 files changed, 22 insertions, 19 deletions
diff --git a/src/VeriFuzz/CodeGen.hs b/src/VeriFuzz/CodeGen.hs index 88a92b6..3a74d94 100644 --- a/src/VeriFuzz/CodeGen.hs +++ b/src/VeriFuzz/CodeGen.hs @@ -240,60 +240,63 @@ render = T.putStrLn . genSource -- Instances instance Source Identifier where - genSource = view getIdentifier + genSource = view getIdentifier instance Source Task where - genSource = genTask + genSource = genTask instance Source Stmnt where - genSource = genStmnt + genSource = genStmnt instance Source PortType where - genSource = genPortType + genSource = genPortType instance Source ConstExpr where - genSource = genConstExpr + genSource = genConstExpr instance Source LVal where - genSource = genLVal + genSource = genLVal instance Source Delay where - genSource = genDelay + genSource = genDelay instance Source Event where - genSource = genEvent + genSource = genEvent instance Source UnaryOperator where - genSource = genUnaryOperator + genSource = genUnaryOperator instance Source Expr where - genSource = genExpr + genSource = genExpr instance Source ContAssign where - genSource = genContAssign + genSource = genContAssign instance Source ModItem where - genSource = genModuleItem + genSource = genModuleItem instance Source PortDir where - genSource = genPortDir + genSource = genPortDir instance Source Port where - genSource = genPort + genSource = genPort instance Source ModDecl where - genSource = genModuleDecl + genSource = genModuleDecl instance Source Description where - genSource = genDescription + genSource = genDescription instance Source VerilogSrc where - genSource = genVerilogSrc + genSource = genVerilogSrc newtype GenVerilog a = GenVerilog { unGenVerilog :: a } instance (Source a) => Show (GenVerilog a) where - show = T.unpack . genSource . unGenVerilog + show = T.unpack . genSource . unGenVerilog instance (Arbitrary a) => Arbitrary (GenVerilog a) where - arbitrary = GenVerilog <$> arbitrary + arbitrary = GenVerilog <$> arbitrary + +instance Source SourceInfo where + genSource (SourceInfo _ src) = genSource src |