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authorYann Herklotz <ymherklotz@gmail.com>2019-02-01 19:34:44 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-02-01 19:34:44 +0000
commita38289ca9d96e97bc4e65b67c50f5805d56a3d86 (patch)
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parentafc9287534bc04ae139fa1d16c80ac0fc55e8767 (diff)
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+{-|
+Module : VeriFuzz.Verilog.Gen
+Description : Various useful generators.
+Copyright : (c) 2019, Yann Herklotz Grave
+License : GPL-3
+Maintainer : ymherklotz [at] gmail [dot] com
+Stability : experimental
+Portability : POSIX
+
+Various useful generators.
+-}
+
+module VeriFuzz.Verilog.Gen where
+
+import qualified Data.Text as T
+import Test.QuickCheck (Arbitrary, Gen, arbitrary)
+import qualified Test.QuickCheck as QC
+import VeriFuzz.Circuit
+import VeriFuzz.Verilog
+
+randomMod :: Gen ModDecl
+randomMod = do
+ let ids = Identifier . ("w"<>) . T.pack . show <$> [1..100]
+ moditems <- sequence $ randomAssigns ids
+ return $ ModDecl "" [] [] []
+
+fromGraph :: Gen ModDecl
+fromGraph = do
+ gr <- QC.generate $ rDups <$> QC.resize 100 (randomCircuit)
+ return $ initMod
+ . head
+ $ (nestUpTo 5 . generateAST $ Circuit gr)
+ ^.. getVerilogSrc
+ . traverse
+ . getDescription