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| author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:35:30 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-19 19:35:30 +0000 |
| commit | 75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b (patch) | |
| tree | f66bf170f9340c86797a623394e63d07ffe66ee8 /src/VeriFuzz/Graph/ASTGen.hs | |
| parent | 4ba440d842e9a0502b429fbc04e2be41c8037a4c (diff) | |
| download | verismith-75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b.tar.gz verismith-75e6abdcb78c70b7449e5fd7f48d8a3e6b3d164b.zip | |
Set column to 100
Diffstat (limited to 'src/VeriFuzz/Graph/ASTGen.hs')
| -rw-r--r-- | src/VeriFuzz/Graph/ASTGen.hs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Graph/ASTGen.hs b/src/VeriFuzz/Graph/ASTGen.hs index 0403f51..ad7dd50 100644 --- a/src/VeriFuzz/Graph/ASTGen.hs +++ b/src/VeriFuzz/Graph/ASTGen.hs @@ -75,8 +75,7 @@ genModuleDeclAST c = ModDecl i output ports items i = Identifier "gen_module" ports = genPortsAST inputsC c output = [Port Wire 90 "y"] - items = - genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] + items = genAssignAST c ++ [ModCA . ContAssign "y" . fold $ portToExpr <$> ports] generateAST :: Circuit -> VerilogSrc generateAST c = VerilogSrc [Description $ genModuleDeclAST c] |