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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-01 20:33:47 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-02-01 20:33:47 +0000 |
commit | 2b690485436b1d4df3c9212a928a1557562fb378 (patch) | |
tree | 4e1275166222b71627d97955213cbcde83154161 /src/VeriFuzz/Internal/AST.hs | |
parent | 157559045f477e443a3f965af6a1959f59930eb8 (diff) | |
download | verismith-2b690485436b1d4df3c9212a928a1557562fb378.tar.gz verismith-2b690485436b1d4df3c9212a928a1557562fb378.zip |
Fix all the compile and test errors
Diffstat (limited to 'src/VeriFuzz/Internal/AST.hs')
-rw-r--r-- | src/VeriFuzz/Internal/AST.hs | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/src/VeriFuzz/Internal/AST.hs b/src/VeriFuzz/Internal/AST.hs new file mode 100644 index 0000000..b8f569b --- /dev/null +++ b/src/VeriFuzz/Internal/AST.hs @@ -0,0 +1,72 @@ +{-| +Module : VeriFuzz.Internal.AST +Description : Defaults and common functions. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Defaults and common functions. +-} + +module VeriFuzz.Internal.AST where + +import Control.Lens +import Data.Text (Text) +import VeriFuzz.AST + +regDecl :: Identifier -> ModItem +regDecl = Decl Nothing . Port (Reg False) 1 + +wireDecl :: Identifier -> ModItem +wireDecl = Decl Nothing . Port Wire 1 + +-- | Create an empty module. +emptyMod :: ModDecl +emptyMod = ModDecl "" [] [] [] + +-- | Set a module name for a module declaration. +setModName :: Text -> ModDecl -> ModDecl +setModName str = modId .~ Identifier str + +-- | Add a input port to the module declaration. +addModPort :: Port -> ModDecl -> ModDecl +addModPort port = modInPorts %~ (:) port + +addDescription :: Description -> VerilogSrc -> VerilogSrc +addDescription desc = getVerilogSrc %~ (:) desc + +testBench :: ModDecl +testBench = ModDecl + "main" + [] + [] + [ regDecl "a" + , regDecl "b" + , wireDecl "c" + , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] + , Initial $ SeqBlock + [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 + , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 + -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" + -- [ Str "%d & %d = %d" + -- , PrimExpr $ PrimId "a" + -- , PrimExpr $ PrimId "b" + -- , PrimExpr $ PrimId "c" + -- ] + -- , SysTaskEnable $ Task "finish" [] + ] + ] + +addTestBench :: VerilogSrc -> VerilogSrc +addTestBench = addDescription $ Description testBench + +defaultPort :: Identifier -> Port +defaultPort = Port Wire 1 + +portToExpr :: Port -> Expr +portToExpr (Port _ _ i) = Id i + +modName :: ModDecl -> Text +modName = view $ modId . getIdentifier |