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| author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 12:37:46 +0000 |
|---|---|---|
| committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 12:37:46 +0000 |
| commit | 928a54419aeac611555b3c15493db00010cbb46e (patch) | |
| tree | 576f1ca4ba287f03700b9526032126302c0474c1 /src/VeriFuzz/Internal/AST.hs | |
| parent | 0ea6e208f2c3c41922f8334174fc8e81a21d67f4 (diff) | |
| download | verismith-928a54419aeac611555b3c15493db00010cbb46e.tar.gz verismith-928a54419aeac611555b3c15493db00010cbb46e.zip | |
Indent by 4
Diffstat (limited to 'src/VeriFuzz/Internal/AST.hs')
| -rw-r--r-- | src/VeriFuzz/Internal/AST.hs | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/VeriFuzz/Internal/AST.hs b/src/VeriFuzz/Internal/AST.hs index 95f3bfc..7866f61 100644 --- a/src/VeriFuzz/Internal/AST.hs +++ b/src/VeriFuzz/Internal/AST.hs @@ -39,16 +39,16 @@ addDescription desc = getVerilogSrc %~ (:) desc testBench :: ModDecl testBench = ModDecl - "main" - [] - [] - [ regDecl "a" - , regDecl "b" - , wireDecl "c" - , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] - , Initial $ SeqBlock - [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 - , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 + "main" + [] + [] + [ regDecl "a" + , regDecl "b" + , wireDecl "c" + , ModInst "and" "and_gate" [ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"] + , Initial $ SeqBlock + [ BlockAssign . Assign (RegId "a") Nothing $ Number 1 1 + , BlockAssign . Assign (RegId "b") Nothing $ Number 1 1 -- , TimeCtrl (Delay 1) . Just . SysTaskEnable $ Task "display" -- [ Str "%d & %d = %d" -- , PrimExpr $ PrimId "a" @@ -56,8 +56,8 @@ testBench = ModDecl -- , PrimExpr $ PrimId "c" -- ] -- , SysTaskEnable $ Task "finish" [] + ] ] - ] addTestBench :: VerilogSrc -> VerilogSrc addTestBench = addDescription $ Description testBench |