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| author | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 18:16:21 +0100 |
| commit | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (patch) | |
| tree | 042f235cdf458e6bf5330a477435d4b34bee7859 /src/VeriFuzz/Internal | |
| parent | 1ef0455ddad821c2ddf64d451e99b8b5508c39c5 (diff) | |
| download | verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.tar.gz verismith-c0c799ab3f79c370e4c33b8f824489ce8b1c96ec.zip | |
Rename to Verilog
Diffstat (limited to 'src/VeriFuzz/Internal')
| -rw-r--r-- | src/VeriFuzz/Internal/AST.hs | 6 | ||||
| -rw-r--r-- | src/VeriFuzz/Internal/Simulator.hs | 2 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/VeriFuzz/Internal/AST.hs b/src/VeriFuzz/Internal/AST.hs index 16d40a3..49e1d30 100644 --- a/src/VeriFuzz/Internal/AST.hs +++ b/src/VeriFuzz/Internal/AST.hs @@ -34,8 +34,8 @@ setModName str = modId .~ Identifier str addModPort :: Port -> ModDecl -> ModDecl addModPort port = modInPorts %~ (:) port -addDescription :: Description -> VerilogSrc -> VerilogSrc -addDescription desc = getVerilogSrc %~ (:) desc +addDescription :: Description -> Verilog -> Verilog +addDescription desc = getVerilog %~ (:) desc testBench :: ModDecl testBench = ModDecl @@ -61,7 +61,7 @@ testBench = ModDecl ] ] -addTestBench :: VerilogSrc -> VerilogSrc +addTestBench :: Verilog -> Verilog addTestBench = addDescription $ Description testBench defaultPort :: Identifier -> Port diff --git a/src/VeriFuzz/Internal/Simulator.hs b/src/VeriFuzz/Internal/Simulator.hs index 9437fab..4c21864 100644 --- a/src/VeriFuzz/Internal/Simulator.hs +++ b/src/VeriFuzz/Internal/Simulator.hs @@ -46,7 +46,7 @@ class (Tool a) => Synthesisor a where -> Sh () -- ^ does not return any values data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text - , runSource :: !VerilogSrc + , runSource :: !Verilog } deriving (Eq, Show) |