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author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 11:41:38 +0000 |
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committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-17 11:41:38 +0000 |
commit | 0ea6e208f2c3c41922f8334174fc8e81a21d67f4 (patch) | |
tree | 3c4889aff5a85f58f7d4db296d7f2f26b8ad031f /src/VeriFuzz/Reduce.hs | |
parent | 08b2b306ae1accfa0b84dc3d327ba54add10a284 (diff) | |
download | verismith-0ea6e208f2c3c41922f8334174fc8e81a21d67f4.tar.gz verismith-0ea6e208f2c3c41922f8334174fc8e81a21d67f4.zip |
Brittany formatting
Diffstat (limited to 'src/VeriFuzz/Reduce.hs')
-rw-r--r-- | src/VeriFuzz/Reduce.hs | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs index e393e51..47cdcac 100644 --- a/src/VeriFuzz/Reduce.hs +++ b/src/VeriFuzz/Reduce.hs @@ -19,10 +19,7 @@ halve :: [a] -> ([a], [a]) halve l = splitAt (length l `div` 2) l removeUninitWires :: [ModItem] -> [ModItem] -removeUninitWires ms = ms - where - ids = ms ^.. traverse . modContAssign . contAssignNetLVal +removeUninitWires ms = ms where ids = ms ^.. traverse . modContAssign . contAssignNetLVal halveModDecl :: ModDecl -> (ModDecl, ModDecl) -halveModDecl m = - (m & modItems %~ fst . halve, m & modItems %~ snd . halve) +halveModDecl m = (m & modItems %~ fst . halve, m & modItems %~ snd . halve) |