diff options
author | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-25 19:59:19 +0000 |
---|---|---|
committer | Yann Herklotz Grave <git@yannherklotzgrave.com> | 2019-02-25 19:59:19 +0000 |
commit | 6daba5fb5523f49ef9965df009a5c276d2d34ccc (patch) | |
tree | 74c535de151cfff92a08a7473d0d553ca65cf026 /src/VeriFuzz/Reduce.hs | |
parent | 79f7d262ed0246ea6556478c611c0db59bb47191 (diff) | |
download | verismith-6daba5fb5523f49ef9965df009a5c276d2d34ccc.tar.gz verismith-6daba5fb5523f49ef9965df009a5c276d2d34ccc.zip |
Add recursive reduce call
Diffstat (limited to 'src/VeriFuzz/Reduce.hs')
-rw-r--r-- | src/VeriFuzz/Reduce.hs | 37 |
1 files changed, 31 insertions, 6 deletions
diff --git a/src/VeriFuzz/Reduce.hs b/src/VeriFuzz/Reduce.hs index 35eea4b..6f11767 100644 --- a/src/VeriFuzz/Reduce.hs +++ b/src/VeriFuzz/Reduce.hs @@ -10,17 +10,42 @@ Portability : POSIX Test case reducer implementation. -} -module VeriFuzz.Reduce where +module VeriFuzz.Reduce + ( halveAssigns + , reduce + ) +where import Control.Lens import VeriFuzz.AST +-- | Split a list in two halves. halve :: [a] -> ([a], [a]) halve l = splitAt (length l `div` 2) l -removeUninitWires :: [ModItem] -> [ModItem] -removeUninitWires ms = ms - where ids = ms ^.. traverse . modContAssign . contAssignNetLVal +-- | Split a module declaration in half by trying to remove assign statements. +halveAssigns :: VerilogSrc -> (VerilogSrc, VerilogSrc) +halveAssigns vsrc = (vsrc & vmod %~ fst . halve, vsrc & vmod %~ snd . halve) + where + vmod = getVerilogSrc . traverse . getDescription . modItems -halveModDecl :: ModDecl -> (ModDecl, ModDecl) -halveModDecl m = (m & modItems %~ fst . halve, m & modItems %~ snd . halve) +-- | Reduce an input to a minimal representation. +reduce :: (VerilogSrc -> IO Bool) -- ^ Failed or not. + -> VerilogSrc -- ^ Input verilog source to be reduced. + -> IO VerilogSrc -- ^ Reduced output. +reduce eval src = do + lresult <- eval l + rresult <- eval r + case (lresult, rresult) of + (True, False) -> + reduce eval l + (False, True) -> + reduce eval r + (True, True) -> + lreduced <- reduce eval l + rreduced <- reduce eval r + return lreduced + _ -> + return src + where + (l, r) = halveAssigns src |