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| author | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:23:03 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-14 20:23:03 +0100 |
| commit | 4caf4003cf3460301709ec6813d71c28456fb5a2 (patch) | |
| tree | 702cd1b7a9564140f75b3f2a356b7d05d97c5cbe /src/VeriFuzz/Sim/Icarus.hs | |
| parent | 0cdf9599b83fd20e297903b0204aec4f390ee98d (diff) | |
| download | verismith-4caf4003cf3460301709ec6813d71c28456fb5a2.tar.gz verismith-4caf4003cf3460301709ec6813d71c28456fb5a2.zip | |
Add bit vector to Icarus simulation
Diffstat (limited to 'src/VeriFuzz/Sim/Icarus.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Icarus.hs | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs index 8876706..d9ec05c 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/VeriFuzz/Sim/Icarus.hs @@ -36,6 +36,7 @@ import Prelude hiding (FilePath) import Shelly import VeriFuzz.Sim.Internal import VeriFuzz.Verilog.AST +import VeriFuzz.Verilog.BitVec import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Internal import VeriFuzz.Verilog.Mutate @@ -65,7 +66,11 @@ addDisplay s = concat $ transpose assignFunc :: [Port] -> ByteString -> Statement assignFunc inp bs = - NonBlockAssign . Assign conc Nothing . Number (B.length bs * 8) $ bsToI bs + NonBlockAssign + . Assign conc Nothing + . Number + . BitVec (B.length bs * 8) + $ bsToI bs where conc = RegConcat (portToExpr <$> inp) convert :: Text -> ByteString |