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author | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-09 12:38:15 +0100 |
commit | d350cd339797c6dd9056afa2b1dad5aed4c31cb9 (patch) | |
tree | 868474f18dfedc05d347cf16d09b5e770bc33293 /src/VeriFuzz/Sim/Icarus.hs | |
parent | 7653f8fd33162b8b166a12e125c988663ec2fe79 (diff) | |
download | verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.tar.gz verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.zip |
Add Parameter type and remove Description
Diffstat (limited to 'src/VeriFuzz/Sim/Icarus.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Icarus.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs index 14023b7..9b5138f 100644 --- a/src/VeriFuzz/Sim/Icarus.hs +++ b/src/VeriFuzz/Sim/Icarus.hs @@ -92,9 +92,9 @@ runSimIcarus sim rinfo bss = do [ Initial $ fold (addDisplay $ assignFunc (_modInPorts m) <$> bss) <> (SysTaskEnable $ Task "finish" []) - ] + ] [] let newtb = instantiateMod m tb - let modWithTb = Verilog $ Description <$> [newtb, m] + let modWithTb = Verilog [newtb, m] writefile "main.v" $ genSource modWithTb runSimWithFile sim "main.v" bss where m = rinfo ^. mainModule |