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author | Yann Herklotz <git@ymhg.org> | 2019-04-02 19:47:32 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-02 19:47:32 +0100 |
commit | fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0 (patch) | |
tree | 673439d49fa095bf3ae9b7bbbca5f30d7ff20838 /src/VeriFuzz/Sim/Internal.hs | |
parent | c0c799ab3f79c370e4c33b8f824489ce8b1c96ec (diff) | |
download | verismith-fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0.tar.gz verismith-fd4b0b5152f94cd406f2e5de86ce7ed0a4d2cbd0.zip |
Large refactor with passing tests
Diffstat (limited to 'src/VeriFuzz/Sim/Internal.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Internal.hs | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs new file mode 100644 index 0000000..e3082b7 --- /dev/null +++ b/src/VeriFuzz/Sim/Internal.hs @@ -0,0 +1,112 @@ +{-| +Module : VeriFuzz.Sim.Internal +Description : Class of the simulator. +Copyright : (c) 2018-2019, Yann Herklotz +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +Class of the simulator and the synthesize tool. +-} + +module VeriFuzz.Sim.Internal + ( Tool(..) + , Simulator(..) + , Synthesisor(..) + , SourceInfo(..) + , mainModule + , rootPath + , timeout + , timeout_ + , bsToI + , noPrint + , echoP + , logger + ) +where + +import Control.Lens +import Data.Bits (shiftL) +import Data.ByteString (ByteString) +import qualified Data.ByteString as B +import Data.Text (Text) +import qualified Data.Text as T +import Prelude hiding (FilePath) +import Shelly +import System.FilePath.Posix (takeBaseName) +import VeriFuzz.Verilog.AST + +-- | Tool class. +class Tool a where + toText :: a -> Text + +-- | Simulation type class. +class (Tool a) => Simulator a where + runSim :: a -- ^ Simulator instance + -> SourceInfo -- ^ Run information + -> [ByteString] -- ^ Inputs to simulate + -> Sh ByteString -- ^ Returns the value of the hash at the output of the testbench. + runSimWithFile :: a + -> FilePath + -> [ByteString] + -> Sh ByteString + +-- | Synthesisor type class. +class (Tool a) => Synthesisor a where + runSynth :: a -- ^ Synthesisor tool instance + -> SourceInfo -- ^ Run information + -> FilePath -- ^ Output verilog file for the module + -> Sh () -- ^ does not return any values + +data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text + , runSource :: !Verilog + } + deriving (Eq, Show) + +-- | May need to change this to Traversal to be safe. For now it will fail when +-- the main has not been properly set with. +mainModule :: Lens' SourceInfo ModDecl +mainModule = lens get_ set_ + where + set_ (SourceInfo top main) v = + SourceInfo top (main & getModule %~ update top v) + update top v m@(ModDecl (Identifier i) _ _ _) | i == top = v + | otherwise = m + get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule + f top (ModDecl (Identifier i) _ _ _) = i == top + +rootPath :: Sh FilePath +rootPath = do + current <- pwd + maybe current fromText <$> get_env "VERIFUZZ_ROOT" + +timeout :: FilePath -> [Text] -> Sh Text +timeout = command1 "timeout" ["300"] . toTextIgnore +{-# INLINE timeout #-} + +timeout_ :: FilePath -> [Text] -> Sh () +timeout_ = command1_ "timeout" ["300"] . toTextIgnore +{-# INLINE timeout_ #-} + +-- | Helper function to convert bytestrings to integers +bsToI :: ByteString -> Integer +bsToI = B.foldl' (\i b -> (i `shiftL` 8) + fromIntegral b) 0 +{-# INLINE bsToI #-} + +noPrint :: Sh a -> Sh a +noPrint = print_stdout False . print_stderr False +{-# INLINE noPrint #-} + +echoP :: Text -> Sh () +echoP t = do + fn <- pwd + echo $ bname fn <> " - " <> t + where bname = T.pack . takeBaseName . T.unpack . toTextIgnore + +logger :: FilePath -> Text -> Sh a -> Sh a +logger fp name = log_stderr_with (l "_log.stderr.txt") + . log_stdout_with (l "_log.txt") + where + l s t = appendFile (file s) (T.unpack t) >> appendFile (file s) "\n" + file s = T.unpack (toTextIgnore $ fp </> fromText name) <> s |