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author | Yann Herklotz <git@ymhg.org> | 2019-04-15 20:37:15 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-04-15 20:37:15 +0100 |
commit | 053be2bd7b06ecb371fa0e163d4d1c3e17fe0df3 (patch) | |
tree | 682785734f9c8447265ae9b2192d54d7860c5619 /src/VeriFuzz/Sim/Internal.hs | |
parent | 705bdb142b1088676ddc3178d8677bd40ab2b1d6 (diff) | |
download | verismith-053be2bd7b06ecb371fa0e163d4d1c3e17fe0df3.tar.gz verismith-053be2bd7b06ecb371fa0e163d4d1c3e17fe0df3.zip |
Move declaration of SourceInfo
Diffstat (limited to 'src/VeriFuzz/Sim/Internal.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Internal.hs | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs index 3264d2e..3ff2924 100644 --- a/src/VeriFuzz/Sim/Internal.hs +++ b/src/VeriFuzz/Sim/Internal.hs @@ -14,8 +14,6 @@ module VeriFuzz.Sim.Internal ( Tool(..) , Simulator(..) , Synthesiser(..) - , SourceInfo(..) - , mainModule , rootPath , timeout , timeout_ @@ -27,7 +25,6 @@ module VeriFuzz.Sim.Internal ) where -import Control.Lens import Control.Monad (void) import Data.Bits (shiftL) import Data.ByteString (ByteString) @@ -63,23 +60,6 @@ class (Tool a) => Synthesiser a where -> FilePath -- ^ Output verilog file for the module -> Sh () -- ^ does not return any values -data SourceInfo = SourceInfo { runMainModule :: {-# UNPACK #-} !Text - , runSource :: !Verilog - } - deriving (Eq, Show) - --- | May need to change this to Traversal to be safe. For now it will fail when --- the main has not been properly set with. -mainModule :: Lens' SourceInfo ModDecl -mainModule = lens get_ set_ - where - set_ (SourceInfo top main) v = - SourceInfo top (main & getModule %~ update top v) - update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v - | otherwise = m - get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule - f top (ModDecl (Identifier i) _ _ _ _) = i == top - rootPath :: Sh FilePath rootPath = do current <- pwd |