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| author | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:48 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-06 21:57:48 +0100 |
| commit | 4b5401ef3400413be0559dfa17718611822fc4c6 (patch) | |
| tree | f57cd74848f1f07454724e1d49369e6847f50ae7 /src/VeriFuzz/Sim/Template.hs | |
| parent | 310171c8891b61958c10a701f4837db3238582a8 (diff) | |
| download | verismith-4b5401ef3400413be0559dfa17718611822fc4c6.tar.gz verismith-4b5401ef3400413be0559dfa17718611822fc4c6.zip | |
Generate flip-flops instead of latches
Diffstat (limited to 'src/VeriFuzz/Sim/Template.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 6bde792..0fc74a0 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -89,7 +89,6 @@ write_verilog -force #{outf} sbyConfig :: (Tool a, Tool b) => FilePath -> a -> Maybe b -> SourceInfo -> Text sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options] mode prove -multiclock on [engines] smtbmc |