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author | Yann Herklotz <git@yannherklotz.com> | 2019-06-17 16:13:00 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-29 16:12:46 +0100 |
commit | a3cf56b7e2edef87181c534dea099a884ac99306 (patch) | |
tree | 8c56694a6dea8b5aa832e8df6fb2eec1620c72f4 /src/VeriFuzz/Sim/Template.hs | |
parent | 54c2072ac4b92bb3db3fcd0208cbb877f1abbf8d (diff) | |
download | verismith-a3cf56b7e2edef87181c534dea099a884ac99306.tar.gz verismith-a3cf56b7e2edef87181c534dea099a884ac99306.zip |
Add part of the simulator implementation
Diffstat (limited to 'src/VeriFuzz/Sim/Template.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 4aa07f6..913b220 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -18,17 +18,19 @@ module VeriFuzz.Sim.Template , xstSynthConfig , vivadoSynthConfig , sbyConfig + , icarusTestbench ) where -import Control.Lens ((^..)) -import Data.Text (Text) -import qualified Data.Text as T -import Prelude hiding (FilePath) +import Control.Lens ((^..)) +import Data.Text (Text) +import qualified Data.Text as T +import Prelude hiding (FilePath) import Shelly -import Text.Shakespeare.Text (st) +import Text.Shakespeare.Text (st) import VeriFuzz.Sim.Internal import VeriFuzz.Verilog.AST +import VeriFuzz.Verilog.CodeGen rename :: Text -> [Text] -> Text rename end entries = @@ -117,3 +119,15 @@ top.v . fromText <$> deps readL = T.intercalate "\n" $ mappend "read -formal " <$> deps + +icarusTestbench :: (Synthesiser a) => Verilog -> a -> Text +icarusTestbench t synth1 = [st| +`include "data/cells_cmos.v" +`include "data/cells_cyclone_v.v" +`include "data/cells_verific.v" +`include "data/cells_xilinx_7.v" +`include "data/cells_yosys.v" +`include "#{synthOutput synth1}" + +#{genSource t} +|] |