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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 19:54:25 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 19:54:25 +0100 |
| commit | 0afc44989b841fcb99e0af1d1bff79f82e700313 (patch) | |
| tree | 69a53ac5290b6a99e1eaafe28c999a7f54e660b4 /src/VeriFuzz/Sim/Template.hs | |
| parent | 3786929d0025b32852fd2eaa1eb281ed60a1d84b (diff) | |
| download | verismith-0afc44989b841fcb99e0af1d1bff79f82e700313.tar.gz verismith-0afc44989b841fcb99e0af1d1bff79f82e700313.zip | |
Add verilog modules to equivalence checking
Diffstat (limited to 'src/VeriFuzz/Sim/Template.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index bd58b83..0fc74a0 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -110,7 +110,7 @@ top.v |] where mis = src ^.. getSourceId - deps = ["cells_cmos.v", "cells_cyclone_v.v", "cells_verific.v", "cells_xilinx_7.v"] + deps = ["cells_cmos.v", "cells_cyclone_v.v", "cells_verific.v", "cells_xilinx_7.v", "cells_yosys.v"] depList = T.intercalate "\n" $ toTextIgnore |