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| author | Yann Herklotz <git@ymhg.org> | 2019-05-07 15:01:23 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-07 15:01:23 +0100 |
| commit | e811ba886d9adaed746abe1c9f37c1a87e58a964 (patch) | |
| tree | 7397a9833508654e142b4cce1a62eb22baf5efe7 /src/VeriFuzz/Sim/Vivado.hs | |
| parent | 70497d189ffb8ce8ad582e4eee941e3526eb9d72 (diff) | |
| download | verismith-e811ba886d9adaed746abe1c9f37c1a87e58a964.tar.gz verismith-e811ba886d9adaed746abe1c9f37c1a87e58a964.zip | |
Add support for multiple modules
Had to manually change module names, as Yosys does not change the
module name at instantiation.
This is done using sed.
Diffstat (limited to 'src/VeriFuzz/Sim/Vivado.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Vivado.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index 6ede8b5..1994a57 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -50,7 +50,7 @@ runSynthVivado sim (SourceInfo top src) = do writefile vivadoTcl . vivadoSynthConfig top . toTextIgnore $ synthOutput sim writefile "rtl.v" $ genSource src - run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) module/;", "-i", "rtl.v"] + run_ "sed" ["s/^module/(* use_dsp=\"no\" *) module/;", "-i", "rtl.v"] echoP "Vivado: run" execute_ SynthFail dir |