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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 18:26:56 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 18:26:56 +0100 |
| commit | a640c7e87b0891402c5e51d8b96cac91d6ab1570 (patch) | |
| tree | 18cfb7f617b56eb0dcbe29d5d3035a6f7391d9f0 /src/VeriFuzz/Sim/Vivado.hs | |
| parent | 29804187ac1aeb6d53985e11e9591dc52633bac0 (diff) | |
| download | verismith-a640c7e87b0891402c5e51d8b96cac91d6ab1570.tar.gz verismith-a640c7e87b0891402c5e51d8b96cac91d6ab1570.zip | |
Add quick fix to run without dsp48
Diffstat (limited to 'src/VeriFuzz/Sim/Vivado.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Vivado.hs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs index fef0c83..0bfbd11 100644 --- a/src/VeriFuzz/Sim/Vivado.hs +++ b/src/VeriFuzz/Sim/Vivado.hs @@ -39,10 +39,11 @@ runSynthVivado sim (SourceInfo top src) outf = do dir <- pwd writefile vivadoTcl . vivadoSynthConfig top $ toTextIgnore outf writefile "rtl.v" $ genSource src + run_ "sed" ["s/^module/(* use_dsp48=\"no\" *) module/;", "-i", "rtl.v"] echoP "Vivado: run" logger_ dir "vivado" $ timeout (vivadoPath sim) ["-mode", "batch", "-source", toTextIgnore vivadoTcl] echoP "Vivado: done" - where vivadoTcl = "vivado_" <> fromText top <.> "tcl" + where vivadoTcl = fromText ("vivado_" <> top) <.> "tcl" |