aboutsummaryrefslogtreecommitdiffstats
path: root/src/VeriFuzz/Sim/XST.hs
diff options
context:
space:
mode:
authorYann Herklotz <git@ymhg.org>2019-05-07 21:20:19 +0100
committerYann Herklotz <git@ymhg.org>2019-05-07 21:20:19 +0100
commit08f2731b97abb6d502422a701276d38e316021ab (patch)
tree837406112c445fabb63e83e468698b3ef3065049 /src/VeriFuzz/Sim/XST.hs
parentdb5c1a788e86d52b75ac237270bf2cabcbd296e6 (diff)
downloadverismith-08f2731b97abb6d502422a701276d38e316021ab.tar.gz
verismith-08f2731b97abb6d502422a701276d38e316021ab.zip
Add configuration options for all simulators
Diffstat (limited to 'src/VeriFuzz/Sim/XST.hs')
-rw-r--r--src/VeriFuzz/Sim/XST.hs27
1 files changed, 16 insertions, 11 deletions
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 92dcaa1..e1e8243 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -18,6 +18,7 @@ module VeriFuzz.Sim.XST
)
where
+import Data.Text (Text, unpack)
import Prelude hiding (FilePath)
import Shelly
import Shelly.Lifted (liftSh)
@@ -27,17 +28,17 @@ import VeriFuzz.Sim.Template
import VeriFuzz.Verilog.AST
import VeriFuzz.Verilog.CodeGen
-data XST = XST { xstPath :: {-# UNPACK #-} !FilePath
- , netgenPath :: {-# UNPACK #-} !FilePath
- , xstOutput :: {-# UNPACK #-} !FilePath
+data XST = XST { xstBin :: !(Maybe FilePath)
+ , xstDesc :: {-# UNPACK #-} !Text
+ , xstOutput :: {-# UNPACK #-} !FilePath
}
deriving (Eq)
-instance Show XST where
- show _ = "xst"
-
instance Tool XST where
- toText _ = "xst"
+ toText (XST _ t _) = t
+
+instance Show XST where
+ show t = unpack $ toText t
instance Synthesiser XST where
runSynth = runSynthXST
@@ -45,21 +46,25 @@ instance Synthesiser XST where
setSynthOutput (XST a b _) = XST a b
defaultXST :: XST
-defaultXST = XST "xst" "netgen" "syn_xst.v"
+defaultXST = XST Nothing "xst" "syn_xst.v"
runSynthXST :: XST -> SourceInfo -> ResultSh ()
runSynthXST sim (SourceInfo top src) = do
dir <- liftSh pwd
- let exec = execute_ SynthFail dir "xst"
+ let exec n = execute_
+ SynthFail
+ dir
+ "xst"
+ (maybe (fromText n) (</> fromText n) $ xstBin sim)
liftSh $ do
writefile xstFile $ xstSynthConfig top
writefile prjFile [st|verilog work "rtl.v"|]
writefile "rtl.v" $ genSource src
logger "XST: run"
- exec (xstPath sim) ["-ifn", toTextIgnore xstFile]
+ exec "xst" ["-ifn", toTextIgnore xstFile]
liftSh $ logger "XST: netgen"
exec
- (netgenPath sim)
+ "netgen"
[ "-w"
, "-ofmt"
, "verilog"