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| author | Yann Herklotz <git@ymhg.org> | 2019-04-18 18:16:35 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-18 18:16:35 +0100 |
| commit | 97398438902d42b33aef475e3e357781582bec16 (patch) | |
| tree | c027eda3c0167ef5aaacd68167c6aac75aff1f58 /src/VeriFuzz/Sim/XST.hs | |
| parent | 7053c6117f39d39852b3259c677691b5df6e7c04 (diff) | |
| download | verismith-97398438902d42b33aef475e3e357781582bec16.tar.gz verismith-97398438902d42b33aef475e3e357781582bec16.zip | |
Add output path to each simulator
Diffstat (limited to 'src/VeriFuzz/Sim/XST.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/XST.hs | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs index 488c404..b5b1b8b 100644 --- a/src/VeriFuzz/Sim/XST.hs +++ b/src/VeriFuzz/Sim/XST.hs @@ -29,6 +29,7 @@ import VeriFuzz.Verilog.CodeGen data XST = XST { xstPath :: {-# UNPACK #-} !FilePath , netgenPath :: {-# UNPACK #-} !FilePath + , xstOutput :: {-# UNPACK #-} !FilePath } deriving (Eq) @@ -40,9 +41,11 @@ instance Tool XST where instance Synthesiser XST where runSynth = runSynthXST + synthOutput = xstOutput + setSynthOutput (XST a b _) f = XST a b f defaultXST :: XST -defaultXST = XST "xst" "netgen" +defaultXST = XST "xst" "netgen" "xst/syn_xst.v" runSynthXST :: XST -> SourceInfo -> FilePath -> ResultSh () runSynthXST sim (SourceInfo top src) outf = do |