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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 17:30:31 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 17:30:31 +0100 |
| commit | 9b4ff9bf2a5356b0603fe46cc45f9724bfbef341 (patch) | |
| tree | 0cc15fc577768653958757b5fc6326a03402db6a /src/VeriFuzz/Sim/XST.hs | |
| parent | 72a6f29c7b1357fbeca70097c84138c6cf6d5e2a (diff) | |
| download | verismith-9b4ff9bf2a5356b0603fe46cc45f9724bfbef341.tar.gz verismith-9b4ff9bf2a5356b0603fe46cc45f9724bfbef341.zip | |
Fix to the logger
Diffstat (limited to 'src/VeriFuzz/Sim/XST.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/XST.hs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs index 359b587..9019db8 100644 --- a/src/VeriFuzz/Sim/XST.hs +++ b/src/VeriFuzz/Sim/XST.hs @@ -28,13 +28,13 @@ import VeriFuzz.Verilog.CodeGen data XST = XST { xstPath :: {-# UNPACK #-} !FilePath , netgenPath :: {-# UNPACK #-} !FilePath } - deriving (Eq, Show) + deriving (Eq, Show) instance Tool XST where - toText _ = "xst" + toText _ = "xst" instance Synthesisor XST where - runSynth = runSynthXST + runSynth = runSynthXST defaultXST :: XST defaultXST = XST "xst" "netgen" @@ -46,9 +46,9 @@ runSynthXST sim (SourceInfo top src) outf = do writefile prjFile [st|verilog work "rtl.v"|] writefile "rtl.v" $ genSource src echoP "XST: run" - _ <- logger dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile] + logger_ dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile] echoP "XST: netgen" - _ <- logger dir "netgen" $ run + logger_ dir "netgen" $ run (netgenPath sim) [ "-w" , "-ofmt" @@ -65,6 +65,6 @@ runSynthXST sim (SourceInfo top src) outf = do ] echoP "XST: done" where - modFile = fromText top + modFile = "xst_" <> fromText top xstFile = modFile <.> "xst" prjFile = modFile <.> "prj" |