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author | Yann Herklotz <git@yannherklotz.com> | 2019-05-25 21:10:45 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-05-25 21:23:48 +0100 |
commit | e4181b3f672040c2478d00ce4c9cd9b0c2cde473 (patch) | |
tree | ff77646ea491e17b03711bdc3a29c2218ecf6e17 /src/VeriFuzz/Sim/Yosys.hs | |
parent | 03755364ff17e5bd6cf6408d982df748fa13376c (diff) | |
download | verismith-e4181b3f672040c2478d00ce4c9cd9b0c2cde473.tar.gz verismith-e4181b3f672040c2478d00ce4c9cd9b0c2cde473.zip |
Add timeout error to synthesisers
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 472af1f..3729a1e 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -62,11 +62,12 @@ yosysPath :: Yosys -> FilePath yosysPath sim = maybe (fromText "yosys") (</> fromText "yosys") $ yosysBin sim runSynthYosys :: Yosys -> SourceInfo -> ResultSh () -runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do - dir <- pwd - writefile inpf $ genSource src - logCommand_ dir "yosys" $ timeout - (yosysPath sim) +runSynthYosys sim (SourceInfo _ src) = do + dir <- liftSh $ do + dir' <- pwd + writefile inpf $ genSource src + return dir' + execute_ SynthFail dir "yosys" (yosysPath sim) [ "-p" , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out ] |