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author | Yann Herklotz <git@ymhg.org> | 2019-05-07 21:20:19 +0100 |
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committer | Yann Herklotz <git@ymhg.org> | 2019-05-07 21:20:19 +0100 |
commit | 08f2731b97abb6d502422a701276d38e316021ab (patch) | |
tree | 837406112c445fabb63e83e468698b3ef3065049 /src/VeriFuzz/Sim/Yosys.hs | |
parent | db5c1a788e86d52b75ac237270bf2cabcbd296e6 (diff) | |
download | verismith-08f2731b97abb6d502422a701276d38e316021ab.tar.gz verismith-08f2731b97abb6d502422a701276d38e316021ab.zip |
Add configuration options for all simulators
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
-rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 50c9759..b2ad5cb 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -21,7 +21,7 @@ module VeriFuzz.Sim.Yosys where import Control.Lens -import Data.Text +import Data.Text (Text, unpack) import Prelude hiding (FilePath) import Shelly import Shelly.Lifted (liftSh) @@ -32,35 +32,39 @@ import VeriFuzz.Verilog.AST import VeriFuzz.Verilog.CodeGen import VeriFuzz.Verilog.Mutate -data Yosys = Yosys { yosysPath :: {-# UNPACK #-} !FilePath - , yosysDescription :: {-# UNPACK #-} !Text - , yosysOutput :: {-# UNPACK #-} !FilePath +data Yosys = Yosys { yosysBin :: {-# UNPACK #-} !(Maybe FilePath) + , yosysDesc :: {-# UNPACK #-} !Text + , yosysOutput :: {-# UNPACK #-} !FilePath } deriving (Eq) instance Tool Yosys where - toText (Yosys _ t _) = t + toText (Yosys _ t _) = t + +instance Show Yosys where + show t = unpack $ toText t instance Synthesiser Yosys where runSynth = runSynthYosys synthOutput = yosysOutput setSynthOutput (Yosys a b _) = Yosys a b -instance Show Yosys where - show _ = "yosys" - defaultYosys :: Yosys -defaultYosys = Yosys "yosys" "syn_yosys.v" "yosys" +defaultYosys = Yosys Nothing "yosys" "syn_yosys.v" + +yosysPath :: Yosys -> FilePath +yosysPath sim = maybe (fromText "yosys") (</> fromText "yosys") $ yosysBin sim runSynthYosys :: Yosys -> SourceInfo -> ResultSh () runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do dir <- pwd writefile inpf $ genSource src logger "Yosys: synthesis" - logCommand_ dir "yosys" - $ timeout - (yosysPath sim) - ["-p", "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out] + logCommand_ dir "yosys" $ timeout + (yosysPath sim) + [ "-p" + , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out + ] logger "Yosys: synthesis done" where inpf = "rtl.v" |