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| author | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:52:20 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-06-05 13:52:27 +0100 |
| commit | 720fa7a822a077458cf0b29e9dcdc754a881e8bd (patch) | |
| tree | fa00db795c17bba78b02de2823c1092fae1d81ec /src/VeriFuzz/Sim/Yosys.hs | |
| parent | f3268d934a9a2b01633b5f7a3353d1a97c40a9df (diff) | |
| download | verismith-720fa7a822a077458cf0b29e9dcdc754a881e8bd.tar.gz verismith-720fa7a822a077458cf0b29e9dcdc754a881e8bd.zip | |
Format all files
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 3729a1e..02a00d5 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -67,7 +67,11 @@ runSynthYosys sim (SourceInfo _ src) = do dir' <- pwd writefile inpf $ genSource src return dir' - execute_ SynthFail dir "yosys" (yosysPath sim) + execute_ + SynthFail + dir + "yosys" + (yosysPath sim) [ "-p" , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out ] |