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| author | Yann Herklotz <git@ymhg.org> | 2019-04-23 13:33:52 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-23 13:33:52 +0100 |
| commit | 78e70ea4382af2ab093facda0657b7bd3fa2ff01 (patch) | |
| tree | 6e87fc85d3365a87c0437c73ab5524434b0e0043 /src/VeriFuzz/Sim/Yosys.hs | |
| parent | 19955b197a0a70d626c2e3c27dc91aabcb8b3e6a (diff) | |
| download | verismith-78e70ea4382af2ab093facda0657b7bd3fa2ff01.tar.gz verismith-78e70ea4382af2ab093facda0657b7bd3fa2ff01.zip | |
Formatting files and add result type to front end
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index f219e01..f72fb1a 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -66,8 +66,7 @@ runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do out = toTextIgnore $ synthOutput sim runMaybeSynth :: (Synthesiser a) => Maybe a -> SourceInfo -> ResultSh () -runMaybeSynth (Just sim) srcInfo = - runSynth sim srcInfo +runMaybeSynth (Just sim) srcInfo = runSynth sim srcInfo runMaybeSynth Nothing (SourceInfo _ src) = liftSh . writefile "rtl.v" $ genSource src |