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| author | Yann Herklotz <git@ymhg.org> | 2019-05-07 15:01:23 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-05-07 15:01:23 +0100 |
| commit | e811ba886d9adaed746abe1c9f37c1a87e58a964 (patch) | |
| tree | 7397a9833508654e142b4cce1a62eb22baf5efe7 /src/VeriFuzz/Sim/Yosys.hs | |
| parent | 70497d189ffb8ce8ad582e4eee941e3526eb9d72 (diff) | |
| download | verismith-e811ba886d9adaed746abe1c9f37c1a87e58a964.tar.gz verismith-e811ba886d9adaed746abe1c9f37c1a87e58a964.zip | |
Add support for multiple modules
Had to manually change module names, as Yosys does not change the
module name at instantiation.
This is done using sed.
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index f72fb1a..1bff975 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -104,7 +104,6 @@ runEquiv -> SourceInfo -> ResultSh () runEquiv _ sim1 sim2 srcInfo = do - root <- liftSh rootPath dir <- liftSh pwd liftSh $ do writefile "top.v" @@ -113,7 +112,9 @@ runEquiv _ sim1 sim2 srcInfo = do . makeTopAssert $ srcInfo ^. mainModule - writefile "test.sby" $ sbyConfig root sim1 sim2 srcInfo + replaceMods (synthOutput sim1) "_1" srcInfo + replaceMods (maybe "rtl.v" synthOutput sim2) "_2" srcInfo + writefile "test.sby" $ sbyConfig sim1 sim2 srcInfo liftSh $ echoP "Running SymbiYosys" execute_ EquivFail dir "symbiyosys" "sby" ["-f", "test.sby"] liftSh $ echoP "SymbiYosys equivalence check passed" |