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| author | Yann Herklotz <git@yannherklotz.com> | 2019-08-29 15:44:33 +1000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2019-08-29 15:44:33 +1000 |
| commit | cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 (patch) | |
| tree | f00baaec9dcb747c27375af366ad9aec9d2dbe16 /src/VeriFuzz/Sim/Yosys.hs | |
| parent | 74a14ef30359e653259bf7139fe806548edefd14 (diff) | |
| download | verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.tar.gz verismith-cccb665ebac6e916c4f961eacbe11a9af7d7ceb3.zip | |
Change name from VeriFuzz to VeriSmith
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 8c73b86..1f583a8 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -1,5 +1,5 @@ {-| -Module : VeriFuzz.Sim.Yosys +Module : VeriSmith.Sim.Yosys Description : Yosys simulator implementation. Copyright : (c) 2018-2019, Yann Herklotz License : BSD-3 @@ -12,7 +12,7 @@ Yosys simulator implementation. {-# LANGUAGE QuasiQuotes #-} -module VeriFuzz.Sim.Yosys +module VeriSmith.Sim.Yosys ( Yosys(..) , defaultYosys , runEquiv @@ -20,20 +20,20 @@ module VeriFuzz.Sim.Yosys ) where -import Control.DeepSeq (NFData, rnf, rwhnf) +import Control.DeepSeq (NFData, rnf, rwhnf) import Control.Lens -import Control.Monad (void) -import Data.Text (Text, unpack) -import Prelude hiding (FilePath) +import Control.Monad (void) +import Data.Text (Text, unpack) +import Prelude hiding (FilePath) import Shelly -import Shelly.Lifted (liftSh) -import Text.Shakespeare.Text (st) -import VeriFuzz.Result -import VeriFuzz.Sim.Internal -import VeriFuzz.Sim.Template -import VeriFuzz.Verilog.AST -import VeriFuzz.Verilog.CodeGen -import VeriFuzz.Verilog.Mutate +import Shelly.Lifted (liftSh) +import Text.Shakespeare.Text (st) +import VeriSmith.Result +import VeriSmith.Sim.Internal +import VeriSmith.Sim.Template +import VeriSmith.Verilog.AST +import VeriSmith.Verilog.CodeGen +import VeriSmith.Verilog.Mutate data Yosys = Yosys { yosysBin :: !(Maybe FilePath) , yosysDesc :: {-# UNPACK #-} !Text |