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| author | Yann Herklotz <git@ymhg.org> | 2019-04-03 17:30:31 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-03 17:30:31 +0100 |
| commit | 9b4ff9bf2a5356b0603fe46cc45f9724bfbef341 (patch) | |
| tree | 0cc15fc577768653958757b5fc6326a03402db6a /src/VeriFuzz/Sim/Yosys.hs | |
| parent | 72a6f29c7b1357fbeca70097c84138c6cf6d5e2a (diff) | |
| download | verismith-9b4ff9bf2a5356b0603fe46cc45f9724bfbef341.tar.gz verismith-9b4ff9bf2a5356b0603fe46cc45f9724bfbef341.zip | |
Fix to the logger
Diffstat (limited to 'src/VeriFuzz/Sim/Yosys.hs')
| -rw-r--r-- | src/VeriFuzz/Sim/Yosys.hs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs index 0d0c98b..2682fe4 100644 --- a/src/VeriFuzz/Sim/Yosys.hs +++ b/src/VeriFuzz/Sim/Yosys.hs @@ -46,7 +46,7 @@ runSynthYosys sim (SourceInfo _ src) outf = do dir <- pwd writefile inpf $ genSource src echoP "Yosys: synthesis" - _ <- logger dir "yosys" + logger_ dir "yosys" $ timeout (yosysPath sim) ["-b", "verilog -noattr", "-o", out, "-S", inp] @@ -102,5 +102,5 @@ runEquiv _ sim1 sim2 srcInfo = do runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|] runMaybeSynth sim2 srcInfo echoP "SymbiYosys: run" - _ <- logger dir "symbiyosys" $ run "sby" ["-f", "test.sby"] + logger_ dir "symbiyosys" $ run "sby" ["-f", "test.sby"] echoP "SymbiYosys: done" |