diff options
| author | Yann Herklotz <git@ymhg.org> | 2019-04-04 15:29:21 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@ymhg.org> | 2019-04-04 15:29:21 +0100 |
| commit | 02019f140184b29735bc8aca17dedb38c0a0a3f1 (patch) | |
| tree | 032d152f54e1e4c4b89a33e3a52691e6e8679d59 /src/VeriFuzz/Sim | |
| parent | 502daf22d4a4c1fcd90020b89506422f2e8b8c17 (diff) | |
| download | verismith-02019f140184b29735bc8aca17dedb38c0a0a3f1.tar.gz verismith-02019f140184b29735bc8aca17dedb38c0a0a3f1.zip | |
Fix for latches in design
Diffstat (limited to 'src/VeriFuzz/Sim')
| -rw-r--r-- | src/VeriFuzz/Sim/Template.hs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/VeriFuzz/Sim/Template.hs b/src/VeriFuzz/Sim/Template.hs index 0fc74a0..6bde792 100644 --- a/src/VeriFuzz/Sim/Template.hs +++ b/src/VeriFuzz/Sim/Template.hs @@ -89,6 +89,7 @@ write_verilog -force #{outf} sbyConfig :: (Tool a, Tool b) => FilePath -> a -> Maybe b -> SourceInfo -> Text sbyConfig bd sim1 sim2 (SourceInfo top src) = [st|[options] mode prove +multiclock on [engines] smtbmc |