Add configuration options for all simulators

4 files changed, 56 insertions, 42 deletions

diff --git a/src/VeriFuzz/Sim/Quartus.hs b/src/VeriFuzz/Sim/Quartus.hs
index 5f3c18c..88bb6c9 100644
--- a/src/VeriFuzz/Sim/Quartus.hs
+++ b/src/VeriFuzz/Sim/Quartus.hs
@@ -16,6 +16,7 @@ module VeriFuzz.Sim.Quartus
     )
 where
 
+import           Data.Text                (Text, unpack)
 import           Prelude                  hiding (FilePath)
 import           Shelly
 import           Shelly.Lifted            (liftSh)
@@ -24,23 +25,24 @@ import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
 data Quartus = Quartus { quartusBin    :: !(Maybe FilePath)
+                       , quartusDesc   :: {-# UNPACK #-} !Text
                        , quartusOutput :: {-# UNPACK #-} !FilePath
                        }
                 deriving (Eq)
 
-instance Show Quartus where
-    show _ = "quartus"
-
 instance Tool Quartus where
-    toText _ = "quartus"
+    toText (Quartus _ t _) = t
+
+instance Show Quartus where
+    show t = unpack $ toText t
 
 instance Synthesiser Quartus where
     runSynth = runSynthQuartus
     synthOutput = quartusOutput
-    setSynthOutput (Quartus a _) = Quartus a
+    setSynthOutput (Quartus a b _) = Quartus a b
 
 defaultQuartus :: Quartus
-defaultQuartus = Quartus Nothing "syn_quartus.v"
+defaultQuartus = Quartus Nothing "quartus" "syn_quartus.v"
 
 runSynthQuartus :: Quartus -> SourceInfo -> ResultSh ()
 runSynthQuartus sim (SourceInfo top src) = do
diff --git a/src/VeriFuzz/Sim/Vivado.hs b/src/VeriFuzz/Sim/Vivado.hs
index bff4d7c..c17334e 100644
--- a/src/VeriFuzz/Sim/Vivado.hs
+++ b/src/VeriFuzz/Sim/Vivado.hs
@@ -16,6 +16,7 @@ module VeriFuzz.Sim.Vivado
     )
 where
 
+import           Data.Text                (Text, unpack)
 import           Prelude                  hiding (FilePath)
 import           Shelly
 import           Shelly.Lifted            (liftSh)
@@ -24,24 +25,25 @@ import           VeriFuzz.Sim.Template
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
-data Vivado = Vivado { vivadoPath   :: {-# UNPACK #-} !FilePath
+data Vivado = Vivado { vivadoBin    :: !(Maybe FilePath)
+                     , vivadoDesc   :: {-# UNPACK #-} !Text
                      , vivadoOutput :: {-# UNPACK #-} !FilePath
                      }
                deriving (Eq)
 
-instance Show Vivado where
-    show _ = "vivado"
-
 instance Tool Vivado where
-    toText _ = "vivado"
+    toText (Vivado _ t _) = t
+
+instance Show Vivado where
+    show t = unpack $ toText t
 
 instance Synthesiser Vivado where
     runSynth = runSynthVivado
     synthOutput = vivadoOutput
-    setSynthOutput (Vivado a _) = Vivado a
+    setSynthOutput (Vivado a b _) = Vivado a b
 
 defaultVivado :: Vivado
-defaultVivado = Vivado "vivado" "syn_vivado.v"
+defaultVivado = Vivado Nothing "vivado" "syn_vivado.v"
 
 runSynthVivado :: Vivado -> SourceInfo -> ResultSh ()
 runSynthVivado sim (SourceInfo top src) = do
@@ -52,10 +54,11 @@ runSynthVivado sim (SourceInfo top src) = do
         writefile "rtl.v" $ genSource src
         run_ "sed" ["s/^module/(* use_dsp=\"no\" *) module/;", "-i", "rtl.v"]
         logger "Vivado: run"
-    execute_ SynthFail
-             dir
-             "vivado"
-             (vivadoPath sim)
-             ["-mode", "batch", "-source", toTextIgnore vivadoTcl]
+    let exec_ n = execute_
+            SynthFail
+            dir
+            "vivado"
+            (maybe (fromText n) (</> fromText n) $ vivadoBin sim)
+    exec_ "vivado" ["-mode", "batch", "-source", toTextIgnore vivadoTcl]
     liftSh $ logger "Vivado: done"
     where vivadoTcl = fromText ("vivado_" <> top) <.> "tcl"
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 92dcaa1..e1e8243 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -18,6 +18,7 @@ module VeriFuzz.Sim.XST
     )
 where
 
+import           Data.Text                (Text, unpack)
 import           Prelude                  hiding (FilePath)
 import           Shelly
 import           Shelly.Lifted            (liftSh)
@@ -27,17 +28,17 @@ import           VeriFuzz.Sim.Template
 import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 
-data XST = XST { xstPath    :: {-# UNPACK #-} !FilePath
-               , netgenPath :: {-# UNPACK #-} !FilePath
-               , xstOutput  :: {-# UNPACK #-} !FilePath
+data XST = XST { xstBin    :: !(Maybe FilePath)
+               , xstDesc   :: {-# UNPACK #-} !Text
+               , xstOutput :: {-# UNPACK #-} !FilePath
                }
          deriving (Eq)
 
-instance Show XST where
-    show _ = "xst"
-
 instance Tool XST where
-    toText _ = "xst"
+    toText (XST _ t _) = t
+
+instance Show XST where
+    show t = unpack $ toText t
 
 instance Synthesiser XST where
     runSynth = runSynthXST
@@ -45,21 +46,25 @@ instance Synthesiser XST where
     setSynthOutput (XST a b _) = XST a b
 
 defaultXST :: XST
-defaultXST = XST "xst" "netgen" "syn_xst.v"
+defaultXST = XST Nothing "xst" "syn_xst.v"
 
 runSynthXST :: XST -> SourceInfo -> ResultSh ()
 runSynthXST sim (SourceInfo top src) = do
     dir <- liftSh pwd
-    let exec = execute_ SynthFail dir "xst"
+    let exec n = execute_
+            SynthFail
+            dir
+            "xst"
+            (maybe (fromText n) (</> fromText n) $ xstBin sim)
     liftSh $ do
         writefile xstFile $ xstSynthConfig top
         writefile prjFile [st|verilog work "rtl.v"|]
         writefile "rtl.v" $ genSource src
         logger "XST: run"
-    exec (xstPath sim) ["-ifn", toTextIgnore xstFile]
+    exec "xst" ["-ifn", toTextIgnore xstFile]
     liftSh $ logger "XST: netgen"
     exec
-        (netgenPath sim)
+        "netgen"
         [ "-w"
         , "-ofmt"
         , "verilog"
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 50c9759..b2ad5cb 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -21,7 +21,7 @@ module VeriFuzz.Sim.Yosys
 where
 
 import           Control.Lens
-import           Data.Text
+import           Data.Text                (Text, unpack)
 import           Prelude                  hiding (FilePath)
 import           Shelly
 import           Shelly.Lifted            (liftSh)
@@ -32,35 +32,39 @@ import           VeriFuzz.Verilog.AST
 import           VeriFuzz.Verilog.CodeGen
 import           VeriFuzz.Verilog.Mutate
 
-data Yosys = Yosys { yosysPath        :: {-# UNPACK #-} !FilePath
-                   , yosysDescription :: {-# UNPACK #-} !Text
-                   , yosysOutput      :: {-# UNPACK #-} !FilePath
+data Yosys = Yosys { yosysBin    :: {-# UNPACK #-} !(Maybe FilePath)
+                   , yosysDesc   :: {-# UNPACK #-} !Text
+                   , yosysOutput :: {-# UNPACK #-} !FilePath
                    }
               deriving (Eq)
 
 instance Tool Yosys where
-  toText (Yosys _ t _) = t
+    toText (Yosys _ t _) = t
+
+instance Show Yosys where
+    show t = unpack $ toText t
 
 instance Synthesiser Yosys where
   runSynth = runSynthYosys
   synthOutput = yosysOutput
   setSynthOutput (Yosys a b _) = Yosys a b
 
-instance Show Yosys where
-    show _ = "yosys"
-
 defaultYosys :: Yosys
-defaultYosys = Yosys "yosys" "syn_yosys.v" "yosys"
+defaultYosys = Yosys Nothing "yosys" "syn_yosys.v"
+
+yosysPath :: Yosys -> FilePath
+yosysPath sim = maybe (fromText "yosys") (</> fromText "yosys") $ yosysBin sim
 
 runSynthYosys :: Yosys -> SourceInfo -> ResultSh ()
 runSynthYosys sim (SourceInfo _ src) = (<?> SynthFail) . liftSh $ do
     dir <- pwd
     writefile inpf $ genSource src
     logger "Yosys: synthesis"
-    logCommand_ dir "yosys"
-        $ timeout
-              (yosysPath sim)
-              ["-p", "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out]
+    logCommand_ dir "yosys" $ timeout
+        (yosysPath sim)
+        [ "-p"
+        , "read -formal " <> inp <> "; synth; write_verilog -noattr " <> out
+        ]
     logger "Yosys: synthesis done"
   where
     inpf = "rtl.v"