Fix to the logger

5 files changed, 23 insertions, 14 deletions

diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index 6bf21f4..14023b7 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -103,8 +103,7 @@ runSimIcarusWithFile :: Icarus -> FilePath -> [ByteString] -> Sh ByteString
 runSimIcarusWithFile sim f _ = do
     dir <- pwd
     echoP "Icarus: Compile"
-    _ <- logger dir "icarus"
-        $ run (icarusPath sim) ["-o", "main", toTextIgnore f]
+    logger_ dir "icarus" $ run (icarusPath sim) ["-o", "main", toTextIgnore f]
     echoP "Icarus: Run"
     B.take 8 . BA.convert . (hash :: ByteString -> Digest SHA256) <$> logger
         dir
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index e3082b7..062035c 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -23,10 +23,12 @@ module VeriFuzz.Sim.Internal
     , noPrint
     , echoP
     , logger
+    , logger_
     )
 where
 
 import           Control.Lens
+import           Control.Monad         (void)
 import           Data.Bits             (shiftL)
 import           Data.ByteString       (ByteString)
 import qualified Data.ByteString       as B
@@ -110,3 +112,11 @@ logger fp name = log_stderr_with (l "_log.stderr.txt")
   where
     l s t = appendFile (file s) (T.unpack t) >> appendFile (file s) "\n"
     file s = T.unpack (toTextIgnore $ fp </> fromText name) <> s
+
+logger_ :: FilePath -> Text -> Sh a -> Sh ()
+logger_ fp name =
+    void . log_stderr_with (l "_log.stderr.txt") . log_stdout_with
+        (l "_log.txt")
+  where
+    l s t = appendFile (file s) (T.unpack t) >> appendFile (file s) "\n"
+    file s = T.unpack (toTextIgnore $ fp </> fromText name) <> s
diff --git a/src/VeriFuzz/Sim/Reduce.hs b/src/VeriFuzz/Sim/Reduce.hs
index bed1169..5684ed5 100644
--- a/src/VeriFuzz/Sim/Reduce.hs
+++ b/src/VeriFuzz/Sim/Reduce.hs
@@ -133,9 +133,9 @@ reduce_
 reduce_ repl eval src = do
     replAnswer <- sequenceA $ evalIfNotEmpty <$> replacement
     case (replacement, replAnswer) of
-        (Single s, Single False) -> runIf s
-        (Dual _ l, Dual True False) -> runIf l
-        (Dual r _, Dual False True) -> runIf r
+        (Single s, Single False    ) -> runIf s
+        (Dual _ l, Dual True False ) -> runIf l
+        (Dual r _, Dual False True ) -> runIf r
         (Dual r l, Dual False False) -> do
             lreduced <- runIf l
             rreduced <- runIf r
@@ -143,7 +143,7 @@ reduce_ repl eval src = do
                 then return lreduced
                 else return rreduced
         (None, None) -> return src
-        _ -> return src
+        _            -> return src
   where
     replacement = repl src
     runIf s = if s /= src then reduce eval s else return s
diff --git a/src/VeriFuzz/Sim/XST.hs b/src/VeriFuzz/Sim/XST.hs
index 359b587..9019db8 100644
--- a/src/VeriFuzz/Sim/XST.hs
+++ b/src/VeriFuzz/Sim/XST.hs
@@ -28,13 +28,13 @@ import           VeriFuzz.Verilog.CodeGen
 data XST = XST { xstPath    :: {-# UNPACK #-} !FilePath
                , netgenPath :: {-# UNPACK #-} !FilePath
                }
-           deriving (Eq, Show)
+         deriving (Eq, Show)
 
 instance Tool XST where
-  toText _ = "xst"
+    toText _ = "xst"
 
 instance Synthesisor XST where
-  runSynth = runSynthXST
+    runSynth = runSynthXST
 
 defaultXST :: XST
 defaultXST = XST "xst" "netgen"
@@ -46,9 +46,9 @@ runSynthXST sim (SourceInfo top src) outf = do
     writefile prjFile [st|verilog work "rtl.v"|]
     writefile "rtl.v" $ genSource src
     echoP "XST: run"
-    _ <- logger dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile]
+    logger_ dir "xst" $ timeout (xstPath sim) ["-ifn", toTextIgnore xstFile]
     echoP "XST: netgen"
-    _ <- logger dir "netgen" $ run
+    logger_ dir "netgen" $ run
         (netgenPath sim)
         [ "-w"
         , "-ofmt"
@@ -65,6 +65,6 @@ runSynthXST sim (SourceInfo top src) outf = do
         ]
     echoP "XST: done"
   where
-    modFile = fromText top
+    modFile = "xst_" <> fromText top
     xstFile = modFile <.> "xst"
     prjFile = modFile <.> "prj"
diff --git a/src/VeriFuzz/Sim/Yosys.hs b/src/VeriFuzz/Sim/Yosys.hs
index 0d0c98b..2682fe4 100644
--- a/src/VeriFuzz/Sim/Yosys.hs
+++ b/src/VeriFuzz/Sim/Yosys.hs
@@ -46,7 +46,7 @@ runSynthYosys sim (SourceInfo _ src) outf = do
     dir <- pwd
     writefile inpf $ genSource src
     echoP "Yosys: synthesis"
-    _ <- logger dir "yosys"
+    logger_ dir "yosys"
         $ timeout
               (yosysPath sim)
               ["-b", "verilog -noattr", "-o", out, "-S", inp]
@@ -102,5 +102,5 @@ runEquiv _ sim1 sim2 srcInfo = do
     runSynth sim1 srcInfo $ fromText [st|syn_#{toText sim1}.v|]
     runMaybeSynth sim2 srcInfo
     echoP "SymbiYosys: run"
-    _ <- logger dir "symbiyosys" $ run "sby" ["-f", "test.sby"]
+    logger_ dir "symbiyosys" $ run "sby" ["-f", "test.sby"]
     echoP "SymbiYosys: done"