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authorYann Herklotz <git@ymhg.org>2019-04-09 12:38:15 +0100
committerYann Herklotz <git@ymhg.org>2019-04-09 12:38:15 +0100
commitd350cd339797c6dd9056afa2b1dad5aed4c31cb9 (patch)
tree868474f18dfedc05d347cf16d09b5e770bc33293 /src/VeriFuzz/Sim
parent7653f8fd33162b8b166a12e125c988663ec2fe79 (diff)
downloadverismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.tar.gz
verismith-d350cd339797c6dd9056afa2b1dad5aed4c31cb9.zip
Add Parameter type and remove Description
Diffstat (limited to 'src/VeriFuzz/Sim')
-rw-r--r--src/VeriFuzz/Sim/Icarus.hs4
-rw-r--r--src/VeriFuzz/Sim/Internal.hs4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/VeriFuzz/Sim/Icarus.hs b/src/VeriFuzz/Sim/Icarus.hs
index 14023b7..9b5138f 100644
--- a/src/VeriFuzz/Sim/Icarus.hs
+++ b/src/VeriFuzz/Sim/Icarus.hs
@@ -92,9 +92,9 @@ runSimIcarus sim rinfo bss = do
[ Initial
$ fold (addDisplay $ assignFunc (_modInPorts m) <$> bss)
<> (SysTaskEnable $ Task "finish" [])
- ]
+ ] []
let newtb = instantiateMod m tb
- let modWithTb = Verilog $ Description <$> [newtb, m]
+ let modWithTb = Verilog [newtb, m]
writefile "main.v" $ genSource modWithTb
runSimWithFile sim "main.v" bss
where m = rinfo ^. mainModule
diff --git a/src/VeriFuzz/Sim/Internal.hs b/src/VeriFuzz/Sim/Internal.hs
index 062035c..925b155 100644
--- a/src/VeriFuzz/Sim/Internal.hs
+++ b/src/VeriFuzz/Sim/Internal.hs
@@ -73,10 +73,10 @@ mainModule = lens get_ set_
where
set_ (SourceInfo top main) v =
SourceInfo top (main & getModule %~ update top v)
- update top v m@(ModDecl (Identifier i) _ _ _) | i == top = v
+ update top v m@(ModDecl (Identifier i) _ _ _ _) | i == top = v
| otherwise = m
get_ (SourceInfo top main) = head . filter (f top) $ main ^.. getModule
- f top (ModDecl (Identifier i) _ _ _) = i == top
+ f top (ModDecl (Identifier i) _ _ _ _) = i == top
rootPath :: Sh FilePath
rootPath = do