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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:53:58 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 15:53:58 +0000 |
commit | c22396d8d80dc090897631ab89a35ab91d0e0c07 (patch) | |
tree | f5acc0a5320a7982c81cc9e96a15b7f948aef2d9 /src/VeriFuzz/Simulator/General.hs | |
parent | 99fe59abc997ba6f65896a2377881409e257faf9 (diff) | |
download | verismith-c22396d8d80dc090897631ab89a35ab91d0e0c07.tar.gz verismith-c22396d8d80dc090897631ab89a35ab91d0e0c07.zip |
Add template file
Diffstat (limited to 'src/VeriFuzz/Simulator/General.hs')
-rw-r--r-- | src/VeriFuzz/Simulator/General.hs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/VeriFuzz/Simulator/General.hs b/src/VeriFuzz/Simulator/General.hs index 3615d3a..538ecaa 100644 --- a/src/VeriFuzz/Simulator/General.hs +++ b/src/VeriFuzz/Simulator/General.hs @@ -38,6 +38,11 @@ class (Simulator a) => Synthesize a where -> FilePath -- ^ Output verilog file for the module -> Sh () -- ^ does not return any values +rootPath :: Sh FilePath +rootPath = do + current <- pwd + maybe current fromText <$> get_env "VERIFUZZ_ROOT" + timeout :: FilePath -> [Text] -> Sh Text timeout = command1 "timeout" ["180"] . toTextIgnore {-# INLINE timeout #-} |