aboutsummaryrefslogtreecommitdiffstats
path: root/src/VeriFuzz/Simulator/Xst.hs
diff options
context:
space:
mode:
authorYann Herklotz <ymherklotz@gmail.com>2019-02-01 19:39:52 +0000
committerYann Herklotz <ymherklotz@gmail.com>2019-02-01 19:39:52 +0000
commit1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad (patch)
tree2c9a8d54bf6f9870f0ae62c150803ccec90d46e7 /src/VeriFuzz/Simulator/Xst.hs
parenta38289ca9d96e97bc4e65b67c50f5805d56a3d86 (diff)
downloadverismith-1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad.tar.gz
verismith-1067284cc1f6ca8ba646545c5b8d0a79cc2e41ad.zip
More restructuring
Diffstat (limited to 'src/VeriFuzz/Simulator/Xst.hs')
-rw-r--r--src/VeriFuzz/Simulator/Xst.hs57
1 files changed, 0 insertions, 57 deletions
diff --git a/src/VeriFuzz/Simulator/Xst.hs b/src/VeriFuzz/Simulator/Xst.hs
deleted file mode 100644
index 52272c3..0000000
--- a/src/VeriFuzz/Simulator/Xst.hs
+++ /dev/null
@@ -1,57 +0,0 @@
-{-|
-Module : VeriFuzz.Simulator.Xst
-Description : Xst (ise) simulator implementation.
-Copyright : (c) 2018-2019, Yann Herklotz Grave
-License : BSD-3
-Maintainer : ymherklotz [at] gmail [dot] com
-Stability : experimental
-Portability : POSIX
-
-Xst (ise) simulator implementation.
--}
-
-{-# LANGUAGE QuasiQuotes #-}
-
-module VeriFuzz.Simulator.Xst where
-
-import Control.Lens hiding ((<.>))
-import qualified Data.Text as T
-import Prelude hiding (FilePath)
-import Shelly
-import System.FilePath.Posix (takeBaseName)
-import Text.Shakespeare.Text (st)
-import VeriFuzz.Simulator.General
-import VeriFuzz.Simulator.Internal.Template
-import VeriFuzz.Verilog
-import VeriFuzz.Verilog
-
-data Xst = Xst { xstPath :: FilePath
- , netgenPath :: FilePath
- }
-
-instance Simulator Xst where
- toText _ = "xst"
-
-instance Synthesize Xst where
- runSynth = runSynthXst
-
-defaultXst :: Xst
-defaultXst =
- Xst "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xst" "/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/netgen"
-
-runSynthXst :: Xst -> ModDecl -> FilePath -> Sh ()
-runSynthXst sim m outf = do
- writefile xstFile $ xstSynthConfig m
- writefile prjFile [st|verilog work "rtl.v"|]
- writefile "rtl.v" $ genSource m
- echoP "Run xst"
- noPrint $ timeout_ (xstPath sim) ["-ifn", toTextIgnore xstFile]
- echoP "Run netgen"
- noPrint $ run_ (netgenPath sim)
- ["-w", "-ofmt", "verilog", toTextIgnore $ modFile <.> "ngc", toTextIgnore outf]
- echoP "Clean synthesized file"
- noPrint $ run_ "sed" ["-i", "/^`ifndef/,/^`endif/ d; s/ *Timestamp: .*//;", toTextIgnore outf]
- where
- modFile = fromText $ modName m
- xstFile = modFile <.> "xst"
- prjFile = modFile <.> "prj"