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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 16:49:17 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-20 16:49:17 +0000 |
commit | d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b (patch) | |
tree | 981c9443c8d919b0bc58abbfb8d617223eb99a9f /src/VeriFuzz/Simulator/Yosys.hs | |
parent | 8cfacbac3bb16fc0294e6eaf7c7b16c238c58d73 (diff) | |
download | verismith-d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b.tar.gz verismith-d60fc9c882f6ce668123fbfbfd9a0f02dd832f7b.zip |
Prettify files
Diffstat (limited to 'src/VeriFuzz/Simulator/Yosys.hs')
-rw-r--r-- | src/VeriFuzz/Simulator/Yosys.hs | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/src/VeriFuzz/Simulator/Yosys.hs b/src/VeriFuzz/Simulator/Yosys.hs index 4c2e0ad..ec5a284 100644 --- a/src/VeriFuzz/Simulator/Yosys.hs +++ b/src/VeriFuzz/Simulator/Yosys.hs @@ -35,10 +35,11 @@ instance Synthesize Yosys where defaultYosys :: Yosys defaultYosys = Yosys "/usr/bin/yosys" -writeSimFile :: Yosys -- ^ Simulator instance - -> ModDecl -- ^ Current module - -> FilePath -- ^ Output sim file - -> Sh () +writeSimFile + :: Yosys -- ^ Simulator instance + -> ModDecl -- ^ Current module + -> FilePath -- ^ Output sim file + -> Sh () writeSimFile _ m file = do writefile "rtl.v" $ genSource m writefile file yosysSimConfig @@ -53,16 +54,19 @@ runSynthYosys sim m outf = do out = toTextIgnore outf -- ids = T.intercalate "," $ allVars m ^.. traverse . getIdentifier -runOtherSynth :: (Synthesize a) => Maybe a -> ModDecl -> Sh () -runOtherSynth (Just sim) m = runSynth sim m $ fromText [st|syn_#{toText sim}.v|] -runOtherSynth Nothing m = writefile "syn_rtl.v" $ genSource m +runMaybeSynth :: (Synthesize a) => Maybe a -> ModDecl -> Sh () +runMaybeSynth (Just sim) m = runSynth sim m $ fromText [st|syn_#{toText sim}.v|] +runMaybeSynth Nothing m = writefile "syn_rtl.v" $ genSource m -runEquiv :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh () -runEquiv yosys sim1 sim2 m = do +runEquivYosys :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh () +runEquivYosys yosys sim1 sim2 m = do writefile "top.v" . genSource . initMod $ makeTop 2 m writefile checkFile $ yosysSatConfig sim1 sim2 m runSynth sim1 m $ fromText [st|syn_#{toText sim1}.v|] - runOtherSynth sim2 m + runMaybeSynth sim2 m run_ (yosysPath yosys) [toTextIgnore checkFile] - where - checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|] + where checkFile = fromText [st|test.#{toText sim1}.#{maybe "rtl" toText sim2}.ys|] + +runEquiv :: (Synthesize a, Synthesize b) => Yosys -> a -> Maybe b -> ModDecl -> Sh () +runEquiv yosys sim1 sim2 m = do + writefile "top.v" . genSource . initMod $ makeTopAssert m |