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author | Yann Herklotz <git@yannherklotz.com> | 2019-09-04 20:15:51 +1000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-09-04 20:15:51 +1000 |
commit | a2b01b92612a098673ff03890e6e8aef4ceb28ea (patch) | |
tree | 15cafe6ba47981938552a4b342a56795251aadc5 /src/VeriFuzz/Verilog.hs | |
parent | cccb665ebac6e916c4f961eacbe11a9af7d7ceb3 (diff) | |
download | verismith-a2b01b92612a098673ff03890e6e8aef4ceb28ea.tar.gz verismith-a2b01b92612a098673ff03890e6e8aef4ceb28ea.zip |
Renaming to VeriSmith
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
-rw-r--r-- | src/VeriFuzz/Verilog.hs | 106 |
1 files changed, 0 insertions, 106 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs deleted file mode 100644 index 6e7851c..0000000 --- a/src/VeriFuzz/Verilog.hs +++ /dev/null @@ -1,106 +0,0 @@ -{-| -Module : VeriSmith.Verilog -Description : Verilog implementation with random generation and mutations. -Copyright : (c) 2019, Yann Herklotz Grave -License : GPL-3 -Maintainer : yann [at] yannherklotz [dot] com -Stability : experimental -Portability : POSIX - -Verilog implementation with random generation and mutations. --} - -{-# LANGUAGE QuasiQuotes #-} - -module VeriSmith.Verilog - ( SourceInfo(..) - , Verilog(..) - , parseVerilog - , GenVerilog(..) - , genSource - -- * Primitives - -- ** Identifier - , Identifier(..) - -- ** Control - , Delay(..) - , Event(..) - -- ** Operators - , BinaryOperator(..) - , UnaryOperator(..) - -- ** Task - , Task(..) - , taskName - , taskExpr - -- ** Left hand side value - , LVal(..) - , regId - , regExprId - , regExpr - , regSizeId - , regSizeRange - , regConc - -- ** Ports - , PortDir(..) - , PortType(..) - , Port(..) - , portType - , portSigned - , portSize - , portName - -- * Expression - , Expr(..) - , ConstExpr(..) - , constToExpr - , exprToConst - , constNum - -- * Assignment - , Assign(..) - , assignReg - , assignDelay - , assignExpr - , ContAssign(..) - , contAssignNetLVal - , contAssignExpr - -- * Statment - , Statement(..) - , statDelay - , statDStat - , statEvent - , statEStat - , statements - , stmntBA - , stmntNBA - , stmntTask - , stmntSysTask - , stmntCondExpr - , stmntCondTrue - , stmntCondFalse - -- * Module - , ModDecl(..) - , modId - , modOutPorts - , modInPorts - , modItems - , ModItem(..) - , modContAssign - , modInstId - , modInstName - , modInstConns - , traverseModItem - , declDir - , declPort - , ModConn(..) - , modConnName - , modExpr - -- * Useful Lenses and Traversals - , getModule - , getSourceId - -- * Quote - , verilog - ) -where - -import VeriSmith.Verilog.AST -import VeriSmith.Verilog.CodeGen -import VeriSmith.Verilog.Parser -import VeriSmith.Verilog.Quote |