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author | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 15:49:13 +0000 |
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committer | Yann Herklotz <ymherklotz@gmail.com> | 2019-01-10 15:49:13 +0000 |
commit | dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9 (patch) | |
tree | e51f51b4e82f3c764bcba88725e20e4fb10284da /src/VeriFuzz/Verilog.hs | |
parent | 3f1190cd7fc873449a1fd430386aa4b773d010ac (diff) | |
download | verismith-dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9.tar.gz verismith-dac34f6ff5c46f11fe6c548b92a02ebf4f10d7e9.zip |
Rename files out of the module
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
-rw-r--r-- | src/VeriFuzz/Verilog.hs | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs new file mode 100644 index 0000000..d88f885 --- /dev/null +++ b/src/VeriFuzz/Verilog.hs @@ -0,0 +1,28 @@ +{-| +Module : Test.VeriFuzz.Verilog +Description : The main verilog module with the syntax and code generation. +Copyright : (c) 2018-2019, Yann Herklotz Grave +License : BSD-3 +Maintainer : ymherklotz [at] gmail [dot] com +Stability : experimental +Portability : POSIX + +The main verilog module with the syntax and code generation. +-} + +module Test.VeriFuzz.Verilog + ( -- * AST + module Test.VeriFuzz.Verilog.AST + -- * Code Generation + , module Test.VeriFuzz.Verilog.CodeGen + -- * Verilog mutations + , module Test.VeriFuzz.Verilog.Mutate + , module Test.VeriFuzz.Verilog.Helpers + , module Test.VeriFuzz.Verilog.Arbitrary + ) where + +import Test.VeriFuzz.Verilog.Arbitrary +import Test.VeriFuzz.Verilog.AST +import Test.VeriFuzz.Verilog.CodeGen +import Test.VeriFuzz.Verilog.Helpers +import Test.VeriFuzz.Verilog.Mutate |