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author | Yann Herklotz <git@yannherklotz.com> | 2019-07-21 13:37:25 +0200 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2019-07-21 13:37:25 +0200 |
commit | 30fbe26f59e54a276f88650ffa5e78343b5411eb (patch) | |
tree | aa3166c423f262ee6296826d2c815a0b54084c31 /src/VeriFuzz/Verilog.hs | |
parent | b5c035e45949945cc62845fa6492cffa77992524 (diff) | |
parent | c19a51a8156bbcaee13d9819c8fe54ed0ca5c4cc (diff) | |
download | verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.tar.gz verismith-30fbe26f59e54a276f88650ffa5e78343b5411eb.zip |
Merge branch 'master' into fix/resize-modports
Diffstat (limited to 'src/VeriFuzz/Verilog.hs')
-rw-r--r-- | src/VeriFuzz/Verilog.hs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/VeriFuzz/Verilog.hs b/src/VeriFuzz/Verilog.hs index 3e8d2c7..628b00a 100644 --- a/src/VeriFuzz/Verilog.hs +++ b/src/VeriFuzz/Verilog.hs @@ -10,6 +10,8 @@ Portability : POSIX Verilog implementation with random generation and mutations. -} +{-# LANGUAGE QuasiQuotes #-} + module VeriFuzz.Verilog ( SourceInfo(..) , Verilog(..) |